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AM29LV800BB-90DTD2

Flash, 512KX16, 90ns, SURF TAPE PACKAGE-44

器件类别:存储    存储   

厂商名称:SPANSION

厂商官网:http://www.spansion.com/

器件标准:

下载文档
器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
SPANSION
零件包装代码
DIE
包装说明
DIE,
针数
44
Reach Compliance Code
compliant
ECCN代码
EAR99
最长访问时间
90 ns
其他特性
EMBEDDED ALGORITHMS; 20 YEAR DATA RETENTION
备用内存宽度
8
启动块
BOTTOM
数据保留时间-最小值
20
JESD-30 代码
R-XUUC-N44
内存密度
8388608 bit
内存集成电路类型
FLASH
内存宽度
16
功能数量
1
端子数量
44
字数
524288 words
字数代码
512000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
512KX16
封装主体材料
UNSPECIFIED
封装代码
DIE
封装形状
RECTANGULAR
封装形式
UNCASED CHIP
并行/串行
PARALLEL
峰值回流温度(摄氏度)
260
编程电压
3 V
认证状态
Not Qualified
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
NO LEAD
端子位置
UPPER
处于峰值回流温度下的最长时间
40
类型
NOR TYPE
文档预览
Am29LV800B
Known Good Die
Data Sheet
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SUPPLEMENT
Am29LV800B Known Good Die
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory—Die Revision 2
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— 2.7 to 3.6 V for read, program, and erase
operations
— Ideal for battery-powered applications
s
Manufactured on 0.32 µm process technology
s
High performance
— 80, 90, or 120 ns access time
s
Low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
s
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 1,000,000 write cycle guarantee
per sector
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
s
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
s
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
s
20-year data retention at 125°C
s
Tested to datasheet specifications at
temperature
s
Quality and reliability levels equivalent to
standard packaged components
Publication#
21356
Rev:
E
Amendment/0
Issue Date:
March 12, 2002
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29LV800B in Known Good Die (KGD) form is
an 8 Mbit, 3.0 volt-only Flash memory. AMD defines
KGD as standard product in die form, tested for function-
ality and speed. AMD KGD products have the same reli-
ability and quality as AMD products in packaged form.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a se ctor simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron injec-
tion.
Am29LV800B Features
The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The word-wide data (x16) appears on DQ15–
DQ0; the byte-wide (x8) data appears on DQ7–DQ0.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. No V
PP
is required for
program or erase operations. The device can also be
programmed in standard EPROM programmers.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
2
Electrical Specifications
Refer to the Am29LV800B data sheet, publication
number 21490, for full electrical specifications on the
Am29LV800B in KGD form.
Am29LV800B Known Good Die
S U P P L E M E N T
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option (V
CC
= 2.7 – 3.6 V)
Max Access Time, t
ACC
(ns)
Max CE# Access, t
CE
(ns)
Max OE# Access, t
OE
(ns)
-80
80
80
30
Am29LV800B KGD
-90
90
90
35
-120
120
120
50
DIE PHOTOGRAPH
DIE PAD LOCATIONS
9
8
7
6
5
4
3
2
1
44 43 42 41 40 39 38 37 36
10
11
12
35
34
33
AMD logo location
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Am29LV800B Known Good Die
3
S U P P L E M E N T
PAD DESCRIPTION
Pads relative to die center.
Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
V
CC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A–1
V
SS
BYTE#
A16
A15
A14
A13
A12
A11
A10
A9
A8
WE#
RESET#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
Pad Center (mils)
X
–0.90
–13.00
–18.90
–24.80
–30.70
–36.50
–42.40
–48.30
–54.20
–63.60
–63.60
–63.60
–63.30
–57.40
–52.00
–46.20
–40.70
–34.90
–29.50
–23.60
–18.10
–8.60
8.70
18.20
23.70
29.50
34.90
40.70
46.20
52.00
57.40
63.30
63.60
63.60
63.60
54.20
46.60
40.70
34.90
28.90
23.10
17.20
11.40
5.40
Y
127.50
127.50
127.50
127.50
127.50
127.50
127.50
127.50
127.50
125.90
115.80
105.70
–126.00
–126.00
–126.00
–126.00
–126.00
–126.00
–125.80
–126.00
–126.00
–129.80
–129.80
–126.00
–126.00
–126.00
–126.00
–126.00
–126.00
–126.00
–126.00
–126.00
105.50
115.60
125.70
129.60
127.50
127.50
127.50
127.50
127.50
127.50
127.50
127.50
Pad Center (millimeters)
X
Y
–0.02
3.24
–0.33
3.24
–0.48
3.24
–0.63
3.24
–0.78
3.24
–0.93
3.24
–1.08
3.24
–1.23
3.24
–1.38
3.24
–1.62
3.20
–1.62
2.94
–1.62
2.68
–1.61
–3.20
–1.46
–3.20
–1.32
–3.20
–1.17
–3.20
–1.03
–3.20
–0.89
–3.20
–0.75
–3.20
–0.60
–3.20
–0.46
–3.20
–0.22
–3.30
0.22
–3.30
0.46
–3.20
0.60
–3.20
0.75
–3.20
0.89
–3.20
1.03
–3.20
1.17
–3.20
1.32
–3.20
1.46
–3.20
1.61
–3.20
1.62
2.68
1.62
2.94
1.62
3.19
1.38
3.29
1.18
3.24
1.03
3.24
0.89
3.24
0.73
3.24
0.59
3.24
0.44
3.24
0.29
3.24
0.14
3.24
Note:
The coordinates above are relative to the die center and can be used to operate wire bonding equipment.
4
Am29LV800B Known Good Die
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