Am29N323D
Data Sheet
(Retired Product)
Am29N323D Cover Sheet
This product has been retired and is not recommended for designs. Please contact your Spansion representative for
alternates. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
23476N
Revision
B
Amendment
10
Issue Date
March 4, 2009
Da ta
Shee t
(Retire d
Pro duct)
This page left intentionally blank.
2
Am29N323D
23476N_B10 March 4, 2009
Am29N323D
32 Megabit (2 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
This product has been retired and is not recommended for designs. Please contact your Spansion representative
for alternates. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■
Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
■
Multiplexed Data and Address for reduced I/O
count
— A0–A15 multiplexed as D0–D15
— Addresses are latched with AVD# control inputs
while CE# low
■
Simultaneous Read/Write operation
— Data can be continuously read from one bank
while executing erase/program functions in other
bank
— Zero latency between read and write operations
■
Read access times at 40 MHz
— Burst access times of 20 ns @ 30 pF
at industrial temperature range
— Asynchronous random access times
of 110 ns @ 30 pF
— Synchronous random access times
of 120 ns @ 30 pF
■
Burst length
— Continuous linear burst
■
Power dissipation (typical values, 8 bits
switching, C
L
= 30 pF)
— Burst Mode Read: 25 mA
— Simultaneous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
■
Sector Architecture
— Eight 4 Kword sectors and sixty-three sectors of
32 Kwords each
— Bank A contains the eight 4 Kword sectors and
fifteen 32 Kword sectors
— Bank B contains forty-eight 32 Kword sectors
■
Sector Protection
— Software command sector locking
— WP# protects the last two boot sectors
— All sectors locked when V
PP
= V
IL
■
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
■
Minimum 1 million erase cycle guarantee
per sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Data# Polling and toggle bits
— Provides a software method of detecting
program and erase operation completion
■
Erase Suspend/Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
■
CMOS compatible inputs, CMOS compatible
outputs
■
Low V
CC
write inhibit
■
Package Option
— 47-ball FBGA
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
23476N
Rev:
B
Amendment/10
Issue Date:
March 4, 2009
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29N323 is a 32 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device,
organized as 2,097,152 words of 16 bits each. This
device uses a single V
CC
of 1.7 to 1.9 V to read, pro-
gram, and erase the memory array. A 12.0-volt V
PP
may be used for faster program performance if desired.
The device can also be programmed in standard
EPROM programmers.
The Am29N323 provides a burst access of 20 ns at 30
pF with initial access times of 120 ns at 30 pF. The
device operates within the industrial temperature range
of –25°C to +85°C. The device is offered in the 47-ball
FBGA package.
tions. For burst operations, the device additionally
requires Power Saving (PS), Ready (RDY), and Clock
(CLK). This implementation allows easy interface with
minimal glue logic to microprocessors/microcontrollers
for high performance read operations.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle
bits). After a program or erase cycle has been com-
pleted, the device automatically returns to reading
array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The device also offers
three types of data protection at the sector level. The
sector lock/unlock command sequence
disables or
re-enables both program and erase operations in any
sector. When at V
IL
,
WP#
locks the two outermost sec-
tors. Finally, when
V
PP
is at V
IL
, all sectors are locked.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device is divided as shown in the following table:
Bank A Sectors
Quantity
8
15
Size
4 Kwords
48
32 Kwords
8 Mbits total
24 Mbits total
32 Kwords
Bank B Sectors
Quantity
Size
The device uses Chip Enable (CE#), Write Enable
(WE#), Address Valid (AVD#) and Output Enable
(OE#) to control asynchronous read and write opera-
2
Am29N323D
March 4, 2009
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package .................... 6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ......................................................9
DQ2: Toggle Bit II ................................................................... 23
Table 5. DQ6 and DQ2 Indications ................................................ 23
Reading Toggle Bits DQ6/DQ2 ............................................... 23
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 24
Table 6. Write Operation Status ..................................................... 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 5. Maximum Negative Overshoot Waveform ...................... 25
Figure 6. Maximum Positive Overshoot Waveform........................ 25
Requirements for Asynchronous Read Operation (Non-Burst) 9
Requirements for Synchronous (Burst) Read Operation .......... 9
Programmable Wait State ...................................................... 10
Power Saving Function ........................................................... 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Input ............................................. 11
Output Disable Mode .............................................................. 11
Hardware Data Protection ...................................................... 11
Low VCC Write Inhibit ............................................................ 12
Write Pulse “Glitch” Protection ............................................... 12
Logical Inhibit .......................................................................... 12
Table 2. Sector Address Table ........................................................13
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Test Setup....................................................................... 27
Table 7. Test Specifications ........................................................... 27
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Input Waveforms and Measurement Levels ................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Synchronous/Burst Read ........................................................ 28
Figure 9. Burst Mode Read ............................................................ 28
Asynchronous Read ............................................................... 29
Figure 10. Asynchronous Mode Read............................................ 29
Figure 11. Reset Timings ............................................................... 30
Erase/Program Operations ..................................................... 31
Figure 12. Program Operation Timings..........................................
Figure 13. Chip/Sector Erase Operations ......................................
Figure 14. Accelerated Unlock Bypass Programming Timing........
Figure 15. Data# Polling Timings (During Embedded Algorithm) ..
Figure 16. Toggle Bit Timings (During Embedded Algorithm)........
Figure 17. Latency with Boundary Crossing ..................................
Figure 18. Initial Access with Power Saving (PS)
Function and Address Boundary Latency ......................................
Figure 19. Initial Access with Address Boundary Latency .............
Figure 20. Example of Five Wait States Insertion ..........................
Figure 21. Back-to-Back Read/Write Cycle Timings ......................
32
33
34
35
35
36
37
38
39
40
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Set Wait State Command Sequence ...................................... 15
Table 3. Third Cycle Address/Data .................................................15
Enable PS (Power Saving) Mode Command Sequence ........ 15
Sector Lock/Unlock Command Sequence .............................. 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 16
Program Command Sequence ............................................... 16
Unlock Bypass Command Sequence ..................................... 16
Figure 1. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 18
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 19
Figure 2. Erase Operation............................................................... 19
Table 4. Command Definitions .......................................................20
Erase and Programming Performance . . . . . . . 41
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42
FDD047—47-Pin Fine-Pitch Ball Grid Array
(FBGA) 7 x 10 mm package ................................................... 42
Mask Set Revision . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A: Daisy Chain Information . . . . . . . . 45
Table 8. Daisy Chain Part for 32Mbit 0.23 µm Flash Products
(FDD047, 7 x 10 mm) ..................................................................... 45
Table 9. FDD047 Package Information .......................................... 45
Table 10. FDD047 Connections ..................................................... 45
Figure 1. FDD047 Daisy Chain Layout
(Top View, Balls Facing Down) ...................................................... 45
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 3. Data# Polling Algorithm ................................................... 21
DQ6: Toggle Bit I .................................................................... 22
Figure 4. Toggle Bit Algorithm......................................................... 22
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
March 4, 2009
Am29N323D
3
