Am70PDL127BDH/Am70PDL129BDH
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
30536
Revision
A
Amendment
+3
Issue Date
November 25, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am70PDL127BDH/Am70PDL129BDH
Stacked Multi-Chip Package (MCP/XIP) Flash Memory,
Data storage MirrorBit Flash, and pSRAM (XIP)
2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and
32 Mbit (2 M x 16-Bit) CMOS Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Consists of Am29PDL127H/Am29PDL129H, 32 Mb
pSRAM and two Am29LV640M.
■
Power supply voltage of 2.7 to 3.3 volt
■
High performance (XIP)
— Access time as fast as 65 ns initial / 25 ns page
■
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
■
Both top and bottom boot blocks in one device
■
Manufactured on 0.13 µm process technology
■
20-year data retention at 125°C
■
Minimum 1 million erase cycle guarantee per sector
■
High performance (Data Storage)
— Access time as fast as 110 ns initial / 30 ns page
■
Package
— 93-Ball FBGA
■
Operating Temperature
— –40°C to +85°C
PERFORMANCE CHARACTERISTICS
■
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 65 ns
Flash Memory Features (XIP)
AM29PDL127H/AM29PDL129H
ARCHITECTURAL ADVANTAGES
■
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
■
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 25 mA program/erase current
— 1 µA typical standby mode current
SOFTWARE FEATURES
■
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■
Dual Chip Enable inputs (PDL129 only)
— Two CE# inputs control selection of each half of the memory
space
■
Single power supply operation
— Full Voltage range: 2.7 to 3.3 volt read, erase, and program
operations for battery-powered applications
■
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
■
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
■
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
PDL127:
—
—
—
—
—
—
—
—
Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank B: 48 Mbit (32 Kw x 96)
Bank C: 48 Mbit (32 Kw x 96)
Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 1A: 48 Mbit (32 Kw x 96)
Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2B: 48 Mbit (32 Kw x 96)
HARDWARE FEATURES
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
cycle completion
PDL129:
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■
WP#/ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and last two 4K
word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a factory
setting
Publication#
30536
Rev:
A
Amendment
+3
Issue Date:
November 25, 2003
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
FLASH MEMORY FEATURES (DATA STORAGE)
AM29LV640M ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 3 V for read, erase, and program operations
■
VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages on the DQ inputs/outputs as
determined by the voltage on the V
IO
pin; operates
from 1.65 to 3.6 V
■
Manufactured on 0.23 µm MirrorBit process
technology
■
SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
■
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■
Minimum 100,000 erase cycle guarantee per sector
■
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■
High performance
— 110 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical effective write buffer word programming
time: 16-word write buffer reduces overall
programming time for multiple-word updates
— 4-word page read buffer
— 16-word write buffer
■
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
SOFTWARE & HARDWARE FEATURES
■
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects first or last sector
regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Hardware reset input (RESET#) resets device
—
Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
pSRAM Features
■
Power dissipation
— Operating: 40 mA maximum
— Standby: 70 µA maximum
— Deep power-down standby: 5 µA
■
CE1s# and CE2ps Chip Select
■
Power down features using CE1s# and CE2ps
■
Data retention supply voltage: 2.7 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■
8-word page mode access
2
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION (PDL129)
The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 8 Mwords. The word-wide data (x16) appears on
DQ15-DQ0. This device can be programmed in-system or in
standard EPROM programmers. A 12.0 V V
PP
is not required
for write or erase operations.
The device offers fast page access time of 25 and 30 ns,
with corresponding random access times of 65 and 85 ns,
respectively, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#f1, CE#f2), write enable
(WE#) and output enable (OE#) controls. Dual Chip Enables
allow access to two 64 Mbit partitions of the 128 Mbit mem-
ory space.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Chip Enable Configuration
CE#f1 Control
Bank 1A
48 Mbit (32 Kw x 96)
Bank 1B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE#f2 Control
Bank 2A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2B
48 Mbit (32 Kw x 96)
Page Mode Features
The page size is 8 words. After initial page access is accom-
plished, the page mode operation provides fast read access
speed of random locations within that page.
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V
to 3.3 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
November 25, 2003
Am70PDL127BDH/Am70PDL129BDH
3
