Am79C978A
PCnet™- Home
Single-Chip 1/10 Mbps PCI Home Networking Controller
DISTINCTIVE CHARACTERISTICS
n
Fully integrated 1 Mbps HomePNA Physical Layer
(PHY) as defined by Home Phoneline Networking
Alliance (HomePNA) specification 1.1
— Optimized for home networking applications
over ordinary copper telephone wire
— In-band control features
— Big endian and little endian byte
alignments supported
— Implements optional PCI power management
event (PME) pin
n
Adjustable power and speed levels
n
32 bits of reserved in-band messaging
piggybacked on Ethernet packet
— Register programmable features
n
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 Ethernet standard
n
Compliant with HomePNA specification 1.1
n
Media Independent Interface (MII) for
connecting external 10/100 Mbps transceivers
— IEEE 802.3u compliant MII
— Intelligent Auto-Poll™ external PHY status
monitor and interrupt
— Supports both auto-negotiable and non-
auto-negotiable external PHYs
— Supports 10BASE-T, 100BASETX/FX,
100BASET4, and 100BASET2 IEEE 802.3
compliant MII PHYs at full-duplex or half-
duplex
n
Power control
n
Performance registers
n
Speed control
n
Major frame timing parameters programmable:
ISBI, AID ISBI, pulse width, inter-symbol time
n
Fully integrated 10 Mbps PHY interface
— Comprehensive Auto-Negotiation
implementation
— Full-duplex capability
— Optimized for 10BASE-T applications
n
Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
33 MHz independent of network clock
— Supports network operation with PCI clock
from 15 MHz to 33 MHz
— High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
— PCI draft specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
— Supports both PCI 5.0-V and 3.3-V
signaling environments
— Plug and Play compatible
— Supports an unlimited PCI burst length
n
Full-duplex operation supported on the MII port
with independent Transmit (TX) and Receive
(RX) channels
n
Supports PC98/PC99 and Net PC specifications
— Implements full OnNow features including
pattern matching and link status wake-up
events
— Implements Magic Packet™ mode
— Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
— Supports PCI Bus Power Management
Interface specification revision 1.1
— Supports Advanced Configuration and Power
Interface (ACPI) specification version 1.0
— Supports Network Device Class Power
Management specification version 1.0a
n
Independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
and RX operations
Publication#
22399
Rev:
C
Amendment/0
Issue Date:
January 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
— RX frame queuing for high latency PCI bus
host operation
— Programmable allocation of buffer space
between RX and TX queues
by allowing protocol analysis to begin before
the end of a receive frame
n
Includes Programmable Inter Packet Gap (IPG) to
address less network aggressive MAC controllers
n
Offers the Modified Back-Off algorithm to
address the
Ethernet Capture Effect
n
IEEE 1149.1-compliant JTAG Boundary Scan test
access port interface and NAND tree test mode
for board-level production connectivity test
n
Software compatible with AMD’s PCnet™
Family and LANCE/C-LANCE register and
descriptor architecture
n
Very low power consumption
n
+3.3 V power supply along with 5 V tolerant I/Os
enable broad system compatibility
n
Available in 144-pin TQFP and 160-pin PQFP
packages
n
Extensive programmable internal/external
loopback capabilities
n
EEPROM interface supports jumperless design
and provides through-chip programming
— Supports full programmability of half-/full-
duplex operation through EEPROM mapping
— Programmable PHY reset output pin capable
of resetting external PHY without the need
for buffering
n
Extensive programmable LED status support
n
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
GENERAL DESCRIPTION
The Am79C978A controller is the first in a series of
home networking products from AMD. The Am79C978A
controller is fabricated in an advanced low power 3.3 V
CMOS process to provide low operating current for
power sensitive applications.
The Am79C978A controller contains an Ethernet Con-
troller based on the Am79C971 Fast Ethernet control-
ler, a physical layer device for supporting the 802.3
standard for 10BASE-T, and a physical layer device for
data networking at speeds up to 1 Mbps over ordinary
residential telephone wiring.
The integrated PCI Ethernet controller is a highly inte-
grated 32-bit full-duplex, 10/100 Mbps Ethernet con-
troller solution designed to address high-performance
system application requirements. It is a flexible bus-
mastering device that can be used in any application,
including network ready PCs. The bus master architec-
ture provides high data throughput and low CPU and
system bus utilization.
The integrated Ethernet transceiver is a physical layer
device suppor ting the IEEE 802.3 standards for
10BASE-T. It provides all of the PHY layer functions
required to support 10 Mbps data transfer speeds.
The integrated HomePNA transceiver is a physical
layer device that enables data networking at speeds up
to 1 Mbps over common residential phone wiring re-
gardless of topology and without disrupting telephone
(POTS) service.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to the PCI local bus, simplifying the de-
sign of an Ethernet or home network node in a PC
system. The device has built-in support for both little
and big endian byte alignment. The integrated home
networking controller’s advanced CMOS design allows
the bus interface to be connected to either a +5.0 V or
a +3.3 V signaling environment. A compliant IEEE
1149.1 JTAG test interface for board level testing is also
provided, as well as a NAND tree test structure for
those systems that do not support the JTAG interface.
The integrated Am79C978A home networking controller
is also compliant with the PC98, PC99, and Net PC spec-
ifications. It includes the full implementation of the Mi-
crosoft OnNow and ACPI specifications, which are
backward compatible with Magic Packet technology, and
is compliant with the PCI Bus Power Management Inter-
face specification by supporting the four power manage-
ment states (D0, D1, D2, and D3), the optional PME pin,
and the necessary configuration and data registers.
The integrated Am79C978A home networking control-
ler is a complete Ethernet or home network node inte-
grated into a single VLSI device. It contains a bus
interface unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 88023 (IEEE 802.3)
compliant Media Access Controller (MAC), a Transmit
FIFO and a large Receive FIFO, and an IEEE 802.3u
compliant MII. Both IEEE 802.3 compliant full-duplex
and half-duplex operations are supported on the MII in-
terface. 10/100 Mbps operation is supported through
the MII interface.
The integrated Am79C978A home networking control-
ler is register compatible with the LANCE (Am7990)
and C-LANCE (Am79C90) Ethernet controllers and all
Ethernet controllers in the PCnet Family (except
I L AC C ™ ( A m 7 9 C 9 0 0 ) ) , i n c l u d i n g P C n e t - I S A
(Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II
(Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI
(Am79C970), PCnet-PCI II (Am79C970A), PCnet-
2
Am79C978A
FAST
(Am79C971), and PCnet-FAST+ (Am79C972).
The Buffer Management Unit supports the LANCE and
PCnet descriptor software models.
The integrated Am79C978A controller supports auto-
configuration in the PCI configuration space. Additional
integrated controller configuration parameters, including
the unique IEEE physical address, can be read from an
external non-volatile memory (EEPROM) immediately
following system reset.
In addition, the Am79C978A controller provides program-
mable on-chip LED drivers for transmit, receive, collision, link
integrity, Magic Packet status, speed, activity, power output,
address match, full-duplex, or 100 Mbps status.
Am79C978A
3
BLOCK DIAGRAM
XTAL1
XTAL2
RXD(3:0)/TXD(3:0)
Clock
Reference
MDIO
MDC
1Mbps HomePNA PHY
MII
Interface
Transmit
State
Machine
Drive
Control
HRTXRXP/N
CLK
RST
AD[31:0]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
MII
Management
Receive
State
Machine
Analog
Front
End
PHY
Control
Link
Monitor
Bus
Rcv
FIFO
PCI Bus
Interface
Unit
MAC
Rcv
FIFO
802.3
MAC
Core
MII
Interface
10 Mbps PHY
12K
SRAM
Transmit
State
Machine
10 BASE-T
TX±
Bus
Xmt
FIFO
MAC
Xmt
FIFO
MDC
MDIO
MII
Management
Receive
State
Machine
RX±
FIFO
Control
Network
Port
Manager
Link
Monitor
Auto
Negotiation
Buffer
Management
Unit
LED
Control
PHY Control
LED0
LED1
LED2
LED3
LED4
EECS
EESK
EEDI
EEDO
TCK
TMS
TDI
TDO
JTAG
Port
Control
OnNow
Power
Management
Unit
93C46
EEPROM
Interface
PME
PG
22399A-1
4
Am79C978A
TABLE OF CONTENTS
AM79C978A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CONNECTION DIAGRAM (160 PQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Magic Packet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Ethernet Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
HomePNA PHY Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
External Crystal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
10/100 Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Am79C978A
5
