AMIS-30523
Product Preview
CAN Micro-Stepping Motor
Driver
Introduction
The AMIS−30523 is a micro−stepping stepper motor driver for
bipolar stepper motors with an embedded CAN transceiver.
The motor driver is connected through I/O pins and a SPI interface
with an external microcontroller. It has an on−chip voltage regulator,
reset−output and watchdog reset, able to supply peripheral devices. It
contains a current−translation table and takes the next micro−step
depending on the clock signal on the “NXT” input pin and the status of
the “DIR” (=direction) register or input pin.
The CAN transceiver is the interface between a (CAN) protocol
controller and the physical bus. It provides differential transmit
capability to the bus and differential receive capability to the CAN
controller. To cope with the long bus delay the communication speed
needs to be low. The integrated transceiver allows low transmit data
rates down 10 kbit/s or lower.
The AMIS−30523 is ideally suited for general−purpose stepper
motor applications in the automotive, industrial, medical, and marine
environment. With the on−chip voltage regulator and embedded CAN
transceiver it further reduces the BOM for mechatronic stepper
applications.
Key Features
Motor Driver
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1
52
QFN52, 8x8
CASE 485M
MARKING DIAGRAM
1
AMIS30523
0C523−001
XXXXYZZ
•
Dual H−Bridge for 2−Phase Stepper Motors
•
Programmable Peak−Current up to 1.2 A Continuous (1.6 A for a
Short Time)*
•
On−Chip Current Translator
•
SPI Interface
•
Seven Step Modes from Full Step up to 32 Micro−Steps
•
PWM Current Control with Automatic Selection of Fast and Slow
ORDERING INFORMATION
Decay and Fully Integrated Current−Sense
See detailed ordering and shipping information in the package
•
Full Output Protection and Diagnosis
dimensions section on page 34 of this data sheet.
•
Thermal Warning and Shutdown
•
Integrated 5 V Regulator to Supply External
•
Low EME: Common−Mode Choke is No Longer
Microcontroller
Required
•
Differential Receiver with Wide common−mode range
CAN Transceiver
($35 V)
•
Compatible with the ISO 11898 Standard
•
Voltage Source via V
SPLIT
Pin for Stabilizing the
•
Wide Range of Bus Communication Speed (0 up to 1
Recessive Bus Level
Mbit/s)
•
No Disturbance of the Bus Lines with an Un−Powered
•
Allows Low Transmit Data Rate in Networks
Node
Exceeding 1 km
•
Logic Level Inputs Compatible with 3.3 V Devices
•
Extremely Low Current Standby Mode with Wake−up
•
These are Pb−Free Devices
via the Bus
*
Output Current Level May be Limited by Ambient Temperature and Heat Sinking
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
0C523−001
XXXX
WL
Y
ZZ
= Specific Device Code
= Date Code
= Wafer Lot
= Assembly Location
= Traceability Code
©
Semiconductor Components Industries, LLC, 2010
November, 2010
−
Rev. P0
1
Publication Order Number:
AMIS−30523/D
AMIS−30523
BLOCK DIAGRAM
VDD
9
46
Timebase
Vreg
CPN CPP VCP
20
40,41
21
22
VBB
25, 26
CLK
Chargepump
CS
DI
DO
NXT
DIR
SLA
POR /WD
CLR
ERR
24
8
45
10
17
19
42
23
Logic &
Registers
SPI
POR
T
R
A
N
S
L
A
T
O
R
EMC
P
W
M
I−
sense
38, 39
MOTXP
OTP
34, 35
MOTXN
Load
Angle
EMC
P
W
M
I−
sense
27, 28
MOTYP
Temp.
Sense
31,32
MOTYN
VCC
4
18
VCC
Band−
gap
POR
V
SPLIT
Thermal
shutdown
7
TxD
52
VCC
V
SPLIT
CANH
CANL
48
STB
51
Mode &
wake
−up
control
Driver
control
49
RxD
GND
6
47
Wake−up
Filter
COMP
COMP
29,30
36, 37
AMIS−30523
Figure 1. Block Diagram AMIS−30523
GND
1, 2
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2
AMIS−30523
POR/WD
TSTO
DO
VDD
GND
CANH
CANL
52
51
50
49
48
47
46
45
44
43
42
41
GND
GND
VCC
RxD
VSPLIT
DI
CLK
NXT
40
STB
TxD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AMIS−30523
VBB
VBB
39
38
37
36
35
34
33
32
31
30
29
28
27
MOTXP
MOTXP
GND
GND
MOTXN
MOTXN
MOTYN
MOTYN
GND
GND
MOTYP
MOTYP
17
18
19
20
21
22
23
24
25
Figure 2. Pin Out AMIS−30523
Table 1. PIN DESCRIPTION
Name
GND
/
VCC
/
RXD
VSPLIT
DI
CLK
NXT
/
DIR
ERRB
SLA
CPN
CPP
VCP
CLR
CSB
VBB
MOTYP
GND
Pin
1, 2
3
4
5
6
7
8
9
10
11 .. 16
17
18
19
20
21
22
23
24
25, 26
27, 28
29, 30
Ground
No function (to be left open in normal operation)
CAN Supply voltage
No function (to be left open in normal operation)
CAN Receive data output; dominant transmitter
³
low output
CAN common−mode stabilization output
SPI Data In
SPI Clock Input
Next micro−step input
No function (to be left open in normal operation)
Direction input
Error output (open drain)
Speed load angle output
Negative connection of charge pump capacitor
Positive connection of charge pump capacitor
Charge pump filter−capacitor
“Clear” = chip reset input
SPI chip select input
High voltage supply Input
Negative end of phase Y coil output
Ground, heat sink
Digital Input
Digital Output
Analog Output
High Voltage
High Voltage
High Voltage
Digital Input
Digital Input
Supply
Driver Output
Supply
Type 1
Type 2
Type 3
Type 2
Type 4
Type 5
Digital Output
Supply
Digital Input
Digital Input
Digital Input
Type 2
Type 2
Type 2
Supply
Description
Type
Supply
Equivalent Schematic
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26
ERR
DIR
CPP
CPN
SLA
VBB
CS
CLR
VCP
VBB
AMIS−30523
Table 1. PIN DESCRIPTION
Name
MOTYN
/
MOTXN
GND
MOTXP
VBB
PORB/WD
TST0
/
DO
VDD
GND
CANH
CANL
/
STB
TXD
Pin
31, 32
33
34, 35
36, 37
38, 39
40, 41
42
43
44
45
46
47
48
49
50
51
52
Description
Positive end of phase Y coil output
No function (to be left open in normal operation)
Positive end of phase X coil output
Ground, heat sink
Negative end of phase X coil output
High voltage supply input
Power−on−reset and watchdog reset output (open drain)
Test pin input (to be tied to ground in normal operation)
No function (to be left open in normal operation)
SPI data output (open drain)
5V Logic Supply Output (needs external decoupling
capacitor)
Ground
High−level CAN bus line (high in dominant mode)
Low−level CAN bus line (low in dominant mode)
No function (to be left open in normal operation)
CAN stand−by mode control input
CAN transmit data input; low input
³
dominant driver;
internal pull−up current
Digital Input
Digital Input
Digital Output
Supply
Supply
Analog Output
Analog Output
Type 4
Type 6
Driver Output
Supply
Driver Output
Supply
Digital Output
Digital Input
Type 3
Type 2
Type
Driver Output
Equivalent Schematic
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
V
BB
V
CC
V
CANH
,
V
CANL
,
V
SPLIT
V
TRANS
T
ST
T
J
V
ESD
V
ESD
V
ESD
V
ESD
V
ESD
Latch−up
Analog DC supply voltage (Note 1)
CAN Supply voltage
DC voltage CANH ,CANL and VSPLIT (Note 2)
Parameter
Min
−0.3
−0.3
−50
Max
+40
+7
+50
Unit
V
V
V
Transient voltage CANH, CANL and VSPLIT (Note 3)
Storage temperature
Junction Temperature under bias (Note 4)
Electrostatic discharges on component level, All pins (Note 5)
Electrostatic discharges on component level, All pins (Note 7)
Electrostatic discharges on CANH, CANL and VSPLIT (Note 6)
Electrostatic discharges on CANH and CANL (Note 7)
Electrostatic discharges on component level, HiV pins (Note 6)
Static latch−up at all pins
−300
−55
−40
−2
−500
−6
−500
−6
+300
+150
+170
+2
+500
+6
+500
+6
100
V
°C
°C
kV
V
kV
V
kV
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For limited time < 0.5 s.
2. For 0 < V
CC
< 5.25 V unlimited time
3. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b.
4. Circuit functionality not guaranteed.
5. Standardized Human body model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).
6. Standardized human body model electrostatic discharge (ESD) pulses (100 pF via 1.5 kW) stressed pin to ground.
7. Standardized charged device model ESD pulses when tested according to ESD STM5.3.1−1999.
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AMIS−30523
Table 3. THERMAL RESISTANCE
Thermal Resistance
Junction−to−Exposed Pad
(Rth
J−EP
)
0.95
Junction−to−Ambient (Rth
J−A
)
1S0P Board
60
2S2P Board
30
Unit
K/W
Package
QFN−52
EQUIVALENT SCHEMATICS
Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
IN
Rpd
4k
OUT
TYPE 1: CLR Input
TYPE 4: DO and ERR Open
Drain Outputs
R
out
SLA
IN
4k
TYPE 2: CLK, DI, CS, NXT, DIR Inputs
VDD
VBB
TYPE 5: SLA Analog Output
VDD
VBB
TYPE 3: V
DD
and V
BB
Power Supply
Figure 3. In− and Output Equivalent Diagrams
PACKAGE THERMAL CHARACTERISTICS
The AMIS−30523 is available in a QFN−52 package. For
cooling optimizations, the QFN has an exposed thermal pad
which has to be soldered to the PCB ground plane. The
ground plane needs thermal vias to conduct the heat to the
bottom layer. Figure 4 gives an example for good power
distribution solutions.
For precise thermal cooling calculations the major
thermal resistances of the device are given. The thermal
media to which the power of the devices has to be given are:
•
Static environmental air (via the case)
•
PCB board copper area (via the exposed pad)
The thermal resistances are presented in Table 5: DC
Parameters Motor Driver.
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rth
J−A
) and the overall Rth
from the junction to exposed pad (Rth
J−EP
). In Table 3 one
can find the values for the Rth
J−A
and Rth
J−EP
, simulated
according to JESD−51:
The Rth
J−A
for 2S2P is simulated conform JEDEC
JESD−51 as follows:
•
A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
•
Board thickness is 1.46 mm (FR4 PCB material)
•
The 2 signal layers: 70
mm
thick copper with an area of
5500 mm
2
copper and 20% conductivity
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