AMIS-42665 High-Speed Low Power CAN Transceiver
Data Sheet
1.0 General Description
The AMIS-42665 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and
may be used in both 12V and 24V systems. The transceiver provides differential transmit capability to the bus and differential receive
capability to the CAN controller.
The AMIS-42665 is a new addition to the CAN high-speed transceiver family and offers the following additional features:
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Ideal passive behaviour when supply voltage is removed
Wake-up over bus
Extremely low current standby mode
Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42665 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of
the output signals.
2.0 Key Features
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•
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•
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Compatible with the ISO 11898 standard (ISO 11898-2, ISO 11898-5 and SAE J2284)
High speed (up to 1Mbaud)
Ideally suited for 12V and 24V industrial and automotive applications
Extremely low current standby mode with wake-up via the bus
Low EME common-mode choke is no longer required
Differential receiver with wide common-mode range (+/- 35V) for high EMS
Voltage source via V
SPLIT
pin for stabilizing the recessive bus level (further EMC improvement)
No disturbance of the bus lines with an un-powered node
Transmit data (TxD) dominant time-out function
Thermal protection
Bus pins protected against transients in an automotive environment
Power down mode in which the transmitter is disabled
Bus and V
SPLIT
pins short circuit proof to supply voltage and ground
Logic level inputs compatible with 3.3V devices
At least 110 nodes can be connected to the same bus.
3.0 Ordering Information
Marketing Name
AMIS42665AGA
AMIS42665ALA
Package
SOIC 150 8 GREEN (JEDEC MS-012)
SOIC 150 8 GREEN (NiPdAu, JEDEC MS-012)
Temp. Range
-40°C…125°C
-40°C…125°C
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AMIS-42665 High-Speed Low Power CAN Transceiver
Data Sheet
4.0 Technical Characteristics
Table 1: Technical Characteristics
Symbol
Parameter
V
CC
Power supply voltage
V
STB
DC voltage at pin STB
V
TxD
DC voltage at pin TxD
V
RxD
DC voltage at pin RxD
V
CANH
DC voltage at pin CANH
V
CANL
DC voltage at pin CANL
V
SPLIT
DC voltage at pin V
SPLIT
V
O(dif)(bus_dom)
Differential bus output voltage in dominant state
CM-range
Input common-mode range for comparator
V
CM-peak
C
load
t
pd(rec-dom)
Symbol
t
pd(dom-rec)
V
CM-step
T
junc
Common-mode peak
Load capacitance on IC outputs
Propagation delay TxD to RxD
Parameter
Propagation delay TxD to RxD
Common-mode step
Junction temperature
Conditions
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
42.5Ω < R
LT
< 60Ω
Guaranteed differential receiver threshold and
leakage current
See Figure 8 and 9 (Note)
See Figure 5
Conditions
See Figure 5
See Figure 8 and 9 (Note)
Min.
4.75
-0.3
-0.3
-0.3
-35
-35
-35
1.5
-35
-500
70
Min.
100
-150
-40
Max.
5.25
V
CC
V
CC
V
CC
+35
+35
+35
3
+35
500
15
230
Max.
245
150
150
Unit
V
V
V
V
V
V
V
V
V
mV
pF
ns
Unit
ns
mV
°C
Note: The parameters V
CM-peak
and V
CM-step
guarantee low EME.
5.0 Block Diagram
V
CC
3
VCC
AMIS-42665
POR
7
TxD
1
Timer
VCC
CANH
V
SPLIT
CANL
Thermal
shutdown
VCC
V
SPLIT
Mode &
wake-up
control
5
STB
8
Driver
control
6
RxD
GND
4
Wake-up
Filter
COMP
2
COMP
PC20050211.1
Figure 1: Block Diagram
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AMIS-42665 High-Speed Low Power CAN Transceiver
6.0 Typical Application
6.1 Application Schematic
Data Sheet
VBAT
IN
5V-reg
OUT
V
CC
STB
8
3
7
V
CC
R
LT
= 60
Ω
CANH
CAN
controller
RxD
4
AMIS-
42665
5
V
SPLIT
C
LT
= 47 nF
CAN
BUS
TxD
1
2
6
CANL
R
LT
= 60
Ω
GND
PC20040829.3
GND
Figure 2: Application Diagram
6.2 Pin Description
TxD
GND
VCC
RxD
1
8
STB
CANH
CANL
V
SPLIT
AMIS-
42665
2
3
4
7
6
5
PC20040829.1
Figure 3: Pin Configuration
Table 2: Pinout
Pin Name Description
1
TxD
Transmit data input; low input => dominant driver; internal pull-up current
2
GND
Ground
3
V
CC
Supply voltage
4
RxD
Receive data output; dominant transmitter => low output
5
V
SPLIT
Common-mode stabilization output
6
CANL Low-level CAN bus line (low in dominant mode)
7
CANH High-level CAN bus line (high in dominant mode)
8
STB
Standby mode control input
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AMIS-42665 High-Speed Low Power CAN Transceiver
7.0 Functional Description
7.1 Operating Modes
Data Sheet
AMIS-42665 provides two modes of operation as illustrated in Table 3. These modes are selectable through pin STB.
Table 3: Operating Modes
Pin
Pin RXD
Mode
STB
Low
High
Normal
Low
Bus dominant
Bus recessive
Standby
High
Wake-up request detected
No wake-up request detected
7.1.1. Normal Mode
In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN
controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME.
7.1.2. Standby Mode
In standby mode both the transmitter and receiver are disabled and a very low-power differential receiver monitors the bus lines for
CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10µA. When a wake-up
request is detected by the low-power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time
period of t
BUS
, the RxD pin is driven low by the transceiver to inform the controller of the wake-up request.
7.2 Split Circuit
The V
SPLIT
pin is operational only in normal mode. In standby mode this pin is floating. The V
SPLIT
is connected as shown in Figure 2 and
its purpose is to provide a stabilized DC voltage of 0.5 x V
CC
to the bus avoiding possible steps in the common-mode signal therefore
reducing EME. These unwanted steps could be caused by an un-powered node on the network with excessive leakage current from the
bus that shifts the recessive voltage from its nominal 0.5 x V
CC
voltage.
7.3 Wake-up
Once a valid wake-up (dominant state longer than t
BUS
) has been received during the standby mode the RxD pin is driven low.
7.4 Over-temperature Detection
A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of
approximately 160°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is
reduced. All other IC functions continue to operate. The transmitter off-state resets when pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
7.5 TxD Dominant Time-out Function
A TxD dominant time-out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network
communication) if pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a
negative edge on pin TxD. If the duration of the low-level on pin TxD exceeds the internal timer value t
dom
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD.
This TxD dominant time-out time (t
dom
)defines the minimum possible bit rate to 40kBaud.
7.6 Fail Safe Features
A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or
negative supply voltage, although power dissipation increases during this fault condition.
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AMIS-42665 High-Speed Low Power CAN Transceiver
Data Sheet
The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 4). Pins TxD and
STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse
supply should the V
CC
supply be removed.
8.0 Electrical Characteristics
8.1 Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin;
sourcing current means the current is flowing out of the pin.
8.2 Absolute Maximum Ratings
Stresses above those listed in the following table may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may effect device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Supply voltage
V
CC
DC voltage at pin CANH
V
CANH
DC voltage at pin CANL
V
CANL
DC voltage at pin VSPLIT
V
SPLIT
DC voltage at pin TxD
V
TxD
DC voltage at pin RxD
V
RxD
DC voltage at pin STB
V
STB
Transient voltage at pin CANH
V
tran(CANH)
Transient voltage at pin CANL
V
tran(CANL)
Transient voltage at pin VSPLIT
V
tran(VSPLIT)
Conditions
Min.
-0.3
-50
-50
-50
-0.3
-0.3
-0.3
-300
-300
-300
Max.
+7
+50
+50
+50
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
+300
+300
+300
Unit
V
V
V
V
V
V
V
V
V
V
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
Note 1
Note 1
Note 1
Note 2
Note 4
Note 2
Note 4
Note 3
V
esd(CANL/CANH/
VSPLIT)
Electrostatic discharge voltage at CANH and CANL pin
Electrostatic discharge voltage at all other pins
Static latch-up at all pins
Storage temperature
Ambient temperature
Maximum junction temperature
-8
-500
-5
-500
-55
-40
-40
+8
+500
+5
+500
120
+150
+125
+170
kV
V
kV
V
mA
°C
°C
°C
V
esd
Latch-up
T
stg
T
amb
T
junc
Notes:
1) Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 4).
2) Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.
3) Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78.
4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
8.3 Thermal Characteristics
Table 5: Thermal Characteristics
Symbol
Parameter
Thermal resistance from junction to ambient in SO8 package
R
th(vj-a)
Thermal resistance from junction to substrate of bare die
R
th(vj-s)
Conditions
In free air
In free air
Value
145
45
Unit
K/W
K/W
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