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AN-6300
FAN6300 / FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant PWM Controller
Abstract
This application note describes a detailed design strategy for
higher-power conversion efficiency and better EMI using a
Quasi-Resonant PWM controller compared to the
conventional, hard-switched converter with a fixed
switching frequency. Based on the proposed design
guideline, a design example with detailed parameters
demonstrates the performance of the controller.
range line voltage and reduces switching loss to minimize
switching voltage on drain of the power MOSFET.
To minimize standby power consumption and improve light-
load efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency and
perform extended valley voltage switching to keep to a
minimum switching voltage.
FAN6300/A/H controller provides many protection
functions. Pulse-by-pulse current limiting ensures the fixed
peak current limit level, even when short-circuit occurs.
Once an open-circuit failure occurs in the feedback loop, the
internal protection circuit disables PWM output
immediately. As long as V
DD
drops below the turn-off
threshold voltage, the controller also disables the PWM
output. The gate output is clamped at 18V to protect the
power MOS from high gate-source voltage conditions. The
minimum t
OFF
time limit prevents the system frequency from
being too high. If the DET pin reaches OVP level, internal
OTP is triggered, and the power system enters latch-mode
until AC power is removed.
Introduction
The highly integrated FAN6300/A/H PWM controller
provides several features to enhance the performance of
flyback converters. FAN6300/A are applied on Quasi-
Resonant flyback converter where maximum operating
frequency is below 100kHz and FAN6300H is suitable for
high frequency operation that is around 190kHz. A built-in
High Voltage (HV) startup circuit can provide more startup
current to reduce the startup time of the controller. Once the
VDD voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce power
consumption. An internal valley voltage detector ensures
power system operates in quasi-resonant operation in wide-
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
AN-6300
APPLICATION NOTE
Figure 1. Basic Quasi-Resonant Converter
HV
8
4.2V
I
HV
27V
Timer
55ms
2ms
30µs
Starter
FB OLP
OVP
VDD
6
Internal
Bias
Two Steps
UVLO
16V/10V/8V
FB
2
Soft-Start
5ms
2R
Latched
R
CS
3
Blanking
Circuit
PWM
Current Limit
I
DET
Latched
0.3V
V
DET
Valley
Detector
1st
Valley
Latched
DET OVP
Internal
OTP
DRV
S
SET
Q
18V
5
GATE
Over-Power
Compensation
R
CLR
Q
(3µs/13µs)
for H version
t
OFF-MIN
(8µs/38µs)
t
OFF-MIN
+9µs
t
OFF-MIN
+5µs
for H version
V
DET
t
OFF
S/H
Blanking
(4µs)
2.5V
(1.5µs) for H version
DET
1
5V
I
DET
0.3V
Latched
4
GND
7
NC
Figure 2. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
2
AN-6300
APPLICATION NOTE
Design Procedure for the Primary-Side Inductance of Transformer
In this section, a design procedure is described using the
schematic of Figure 1 as a reference.
designed to turn on the MOSFET when
V
ds
reaches its
minimum voltage
V
in
-n(V
o
+V
d
).
[a] Define the System Specifications
Line voltage range (V
in,min
and
V
in,max
)
Maximum output power (P
o
).
Output voltage (V
o
) and maximum output current (I
o
)
Estimated efficiency (η)
The power conversion efficiency must be estimated to
calculate the maximum input power. In the case of NB
adaptor applications, the typical efficiency is 85%~90%.
With the estimated efficiency, the maximum input power
is given by:
n:1
+
V
in
n(V
o
+V
d
)
-
+
C
oss
+
V
ds
-
-
+
V
d
-
+
V
o
-
P
in
=
P
o
η
(1)
[b] Estimate Reflected Output Voltage
Figure 3 shows the typical waveforms of the drain voltage
of quasi-resonant flyback converter. When the MOSFET
is turned off, the DC link voltage (V
o
), together with the
output voltage (V
o
) and the forward voltage drop of the
Schottky diode (V
d
) reflected to the primary, are imposed
on the MOSFET. The maximum nominal voltage across
the MOSFET (V
ds
) is:
V
ds
n(V
o
+V
d
)
V
ds
n(V
o
+V
d
)
n(V
o
+V
d
)
V
in,max
n(V
o
+V
d
)
0V
Figure 3. Typical Waveform of MOSFET Drain Voltage
for QR Operation
V
ds,max
=
V
in,max
+ n
(
V
o
+ V
d
)
(2)
I
ds
where the turns ratio of primary to secondary side of
transformer is defined as
n
and
V
ds
is as specified in
Equation 2.
By increasing
n,
the capacitive switching loss and
conduction loss of the MOSFET is reduced. However, this
increases the voltage stress on the MOSFET as shown in
Figure 3. Therefore, determine
n
by a trade-off between
the voltage margin of the MOSFET and the efficiency.
Typically, a turn-off voltage spike of
V
ds
is considered as
100V, thus
V
ds,max
is designed around 490~550V
(75~85% of MOSFET rated voltage).
I
in
I
dspk
I
d
DT
s
[c] Determine the Transformer Primary-side
Inductance (L
P
)
Figure 4 shows the typical waveforms of MOSFET drain
current (I
ds
), secondary diode current (I
d
), and the
MOSFET drain voltage (V
ds
) of a QR converter. During
t
OFF
, the current flows through the secondary side rectifier
diode. When
I
d
reduces to zero,
V
ds
begins to drop by the
resonance between the effective output capacitor of the
MOSFET and the primary-side inductance (L
P
). To
minimize the switching loss, the FAN6300/A/H is
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
3
V
ds
n(V
o
+V
d
)
V
in
+n(V
o
+V
d
)
V
in
n(V
o
+V
d
)
V
in
-n(V
o
+V
d
)
t
OFF
T
S
t
F
t
ON
Figure 4. Typical Waveform of QR Operation
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AN-6300
APPLICATION NOTE
To determine the primary-side inductance (L
P
), the
following variables should be determined beforehand:
The minimum switching frequency (
f
s,min
):
The
maximum average input current occurs at the
minimum input voltage and full-load condition.
Meanwhile, the switching frequency is at minimum
value during QR operation.
The falling time of the MOSFET drain voltage (t
f
):
As shown in Figure 4, the falling time of MOSFET
drain voltage is half of the resonant period of the
MOSFET effective output capacitance and primary-
side inductance. If a resonant capacitor is added to be
paralleled with
C
oss
,
t
f
can be increased and EMI can
be reduced. However, this forces a switching loss
increase. The typical value of
t
f
for NB adaptor
application is about 0.5~1μs.
After determining
f
s,min
and
t
f
, the maximum duty cycle is
calculated as:
[d] Determine the Proper Core and the
Minimum Primary Turns
When designing the transformer, consider the maximum
flux density swing in normal operation (B
max
). The
maximum flux density swing in normal operation is
related to the hysteresis loss in the core, while the
maximum flux density in transient is related to the core
saturation.
From Faraday’s law, the minimum number of turns for the
transformer primary side is given by:
N
P,min
=
L
P
I
ds,max
pk
B
max
A
e
×
10
6
(9)
where:
L
P
is
specified
in
Equation
7;
pk
I
ds,max
is the peak drain current specified in Equation 6;
A
e
is the cross-sectional area of the core in mm
2
; and
B
max
is the maximum flux density swing in tesla.
Generally, it is possible to use
B
max
=0.25~0.30 T.
D
max
=
n
(
V
o
+ V
d
)
n
(
V
o
+ V
d
)
+ V
in
×
(1 - f
s,min
×
t
f
)
(3)
where
V
in,min
is specified at low-line and full-load.
According to Equation 1, the maximum average input
current
I
in,max
is determined as
Determine the Number of Turns for Auxiliary
Winding
The number of turns for auxiliary winding (N
a
) can be
obtained by:
V + V
D1
N
a
=
DD
(10)
V
o
+ V
d
where:
V
DD
is the operating voltage for VDD pin;
V
D1
is the forward voltage drop of
D
1
in Figure 5; and
V
o
and
V
d
as determined in Equation 2.
I
in,max
=
V
o
I
o
V
in,min
η
(4)
According to Figure 3,
I
in,max
can be obtained as:
I
in,max
=
1
2
D
max
I
ds,max
pk
(5)
I
ds,maxpk
can be determined as:
I
ds,max
pk
=
V
in,min
D
max
L
m
f
s,min
(6)
In Equation 5, replace
I
ds,maxpk
by Equation 6, then
combine Equations 4 and 5 to obtain
L
P
:
L
P
=
(V
in,min
D
max
)
2P
in
f
s,min
2
(7)
where
P
in
, and
D
max
are specified in Equations 1 and 3,
respectively, and
f
s,min
is the minimum switching
frequency.
Once
L
P
is determined, the RMS current of the MOSFET
in normal operation are obtained as:
I
ds,max
rms
=
D
max
3
I
ds,max
peak
(8)
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com
4
AN-6300
APPLICATION NOTE
Determine the Startup Circuitry
When the power is turned on, the internal current
(typically 1.2mA) charges the capacitor
C
1
through a
forward diode
D
2
and a startup resistor
R
HV
. During the
startup sequence, the V
AC
from the AC terminal provides a
startup current of about 1.2mA and charges the capacitor
C
1
.
R
HV
and
D
2
series connections can be directly
connected by V
AC
to the HV pin. As the VDD pin reaches
the turn-on threshold voltage V
DD-ON
, the FAN6300/A/H
activates and signals the MOSFET. The HV startup circuit
switches off and
D
1
is turned on when the energy of the
main transformer is delivered to secondary and auxiliary
winding.
V
DD-ON
When the supply current is drawn from the transformer, it
draws a leakage current of about 1μA for the HV pin. The
maximum power dissipation of the
R
HV
is:
P
R
=
I
HV - LC(typ.)
×
R
HV
2
HV
(12)
where
I
HV-LC
is the supply current drawn from the HV pin.
P
R
= 1μA
2
x 100KΩ
≅
0.1μW
HV
(13)
The FAN6300/A/H has a voltage detector on the VDD pin
to ensure that the chip has enough power to drive the
MOSFET. Figure 7 shows a hysteresis of the turn-on and
turn-off threshold levels.
I
DD
4.5mA
V
AC
D
2
R
HV
I
HV
8
t
D-ON
D
1
C
1
80μA
10μA
8V
10V
16V
V
DD
HV
VDD
6
Figure 7. UVLO Specification
FAN630 0/A/H
GND
4
Figure 5. Startup Circuit for Power Transfer
The maximum power-on delay time is determined as:
The turn-on and turn-off threshold voltage are internally
fixed at 16V and 10V. During startup,
C
1
must be charged
to 16V to enable the IC. The capacitor continues to supply
the V
DD
until the energy can be delivered from the
auxiliary winding of the main transformer. The V
DD
must
not drop below 10V during the startup sequence.
If the secondary output short circuits or the feedback loop
is open, the FB pin voltage rises rapidly toward the open-
loop voltage, V
FB-OPEN
. Once the FB voltage remains
above V
FB-OLP
and lasts for t
D-OLP
, the FAN6300/A/H stops
emitting output pulses. To further limit the input power
under short-circuit or open-loop conditions, a special two-
step UVLO mechanism has been built in to prolong this
discharge time of the V
DD
capacitor. In Figure 8, the two-
step UVLO mechanism decreases the operating current
and pulls the V
DD
voltage toward the V
DD-OFF
. This sinking
current is disabled after the V
DD
drops below V
DD-OFF
. The
V
DD
voltage is again charged towards V
DD-ON
. With the
addition of the two-step UVLO mechanism, the average
input power during a short-circuit or open-loop condition
is greatly reduced. When the gate pulses are emitted, the
start-timer t
STARTER
with 30μs per cycle is enabled. The
30μs start timer is enabled during startup until the output
voltage is established, when the feedback voltage (V
FB
) is
larger than 4.2V.
C
×
V
(11)
t
D
−
ON
=
1
DD
−
ON
1.2
mA
where V
DD-ON
is the FAN6300/A/H turn-on threshold
voltage and t
D-ON
is the power-on delay time of the
converter.
If a shorter startup time is required, a two-step startup
circuit, as shown in Figure 6, is recommended. In this
circuit, a smaller
C
1
capacitor can be used to reduce the
startup time. The energy supporting the FAN6300/A/H
after startup is mainly from a larger capacitor
C
2
.
V
DD-ON
V
AC
D
2
R
HV
I
HV
8
t
D-ON
D
1
C
1
4
D
2
C
2
HV
VDD
6
FAN6300/A/H
GND
Figure 6. Two-Step Circuit Providing Power
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
5
Figure 8. FAN6300/A/H UVLO Effect
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