Protection diode only exists at power pin(1,4) output, not
including pin (2,3).
General Description
AH266 is an integrated Hall sensor with output
drivers designed for electronic commutation of
brush-less DC motor applications. The device
includes an on-chip Hall voltage generator for
magnetic sensing, a comparator that amplifies the
Hall voltage, and a Schmitt trigger to provide
switching hysteresis for noise rejection, and
complementary darlington open-collector drivers for
sinking large current loads. An internal bandgap
regulator is used to provide temperature
compensated supply voltage for internal circuits and
allows a wide operating supply range.
If a magnetic flux density (B) is larger than operate
point (Bop), DO turn on (low) and DOB turn off
(high). The outputs state is latched prior to reach
release point (Brp). if B< Brp, DO turn off and DOB
turn on. AH266 is rated for operation over
temperature range from -20
o
C to 85
o
C and voltage
range from 4V to 28V. The devices are available in
low cost die forms or rugged 4 pin SIP packages.
Application
- Dual-coil Brush-less DC Motor
- Dual-coil Brush-less DC Fan
- Revolution Counting
- Speed Measurement
Pin Assignment
4. GND
3. DOB
2. DO
1. VCC
Pin Configuration
Name
VCC
DO
DOB
GND
Description
Positive Power Supply
Output Pin
Output Pin
Ground
Ordering Information
AH266 X - X X X - X
Wafer Body
Blank or
A~Z : if necessary
to specify
Package
P: SIP-4L
Lead
L : Lead Free
Blank: Normal
Packing
Blank : Tube
A : Taping
Magnetic
Characteristics
A or B
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.2 Jan 19, 2005
1/6
AH266
High Voltage Hall Effect Latch
Block Diagram
VCC
1
DO
REG.
Hall
Plate
Amp
DOB
Typical Application Circuit
266
coil1
coil2
1
Vcc
2
3
4
Brush-less DC Fan
Note: This application circuit can’t protect reverse coil current if power is connecting reverse.
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FPGA/CPLD
