AP2RA04GMT-HF
Halogen-Free Product
Advanced Power
Electronics Corp.
▼
Simple Drive Requirement
▼
SO-8 Compatible with Heatsink
▼
Low On-resistance
▼
RoHS Compliant & Halogen-Free
G
N-CHANNEL ENHANCEMENT MODE
POWER MOSFET
D
BV
DSS
R
DS(ON)
I
D
40V
2.9mΩ
130A
D
S
D
D
D
Description
AP2RA04 series are from Advanced Power innovated design and
silicon process technology to achieve the lowest possible on-
resistance and fast switching performance. It provides the designer
with an extreme efficient device for use in a wide range of power
applications.
The PMPAK
®
5x6 package is special for DC-DC converters
application and the foot print is compatible with SO-8 with backside
heat sink and lower profile.
S
S
S
G
PMPAK
®
5x6
®
Absolute Maximum Ratings@T
j
=25
o
C(unless otherwise specified)
Symbol
V
DS
V
GS
I
D
@T
C
=25℃
I
D
@T
A
=25℃
I
D
@T
A
=70℃
I
DM
P
D
@T
C
=25℃
P
D
@T
A
=25℃
E
AS
T
STG
T
J
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current (Chip), V
GS
@ 10V
Drain Current, V
GS
@ 10V
Drain Current, V
GS
@ 10V
Pulsed Drain Current
1
Total Power Dissipation
Total Power Dissipation
Single Pulse Avalanche Energy
4
Storage Temperature Range
Operating Junction Temperature Range
3
3
Rating
40
+20
130
32.5
26
250
83.3
5
28.8
-55 to 150
-55 to 150
Units
V
V
A
A
A
A
W
W
mJ
℃
℃
Thermal Data
Symbol
Rthj-c
Rthj-a
Parameter
Maximum Thermal Resistance, Junction-case
Maximum Thermal Resistance, Junction-ambient
3
Value
1.5
25
Units
℃/W
℃/W
Data & specifications subject to change without notice
1
201501062
AP2RA04GMT-HF
Electrical Characteristics@T
j
=25
o
C(unless otherwise specified)
Symbol
BV
DSS
R
DS(ON)
Parameter
Drain-Source Breakdown Voltage
Static Drain-Source On-Resistance
2
Test Conditions
V
GS
=0V, I
D
=250uA
V
GS
=10V, I
D
=20A
V
GS
=4.5V, I
D
=20A
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
R
g
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current
Gate-Source Leakage
Total Gate Charge
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V
DS
=V
GS
, I
D
=250uA
V
DS
=10V, I
D
=20A
V
DS
=40V, V
GS
=0V
V
GS
=+20V, V
DS
=0V
I
D
=20A
V
DS
=20V
V
GS
=4.5V
V
DS
=20V
I
D
=1A
R
G
=3.3Ω
V
GS
=10V
V
GS
=0V
V
DS
=25V
f=1.0MHz
f=1.0MHz
Min.
40
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-
-
-
80
-
-
26
6
14
10.5
8
27
52
Max. Units
-
2.9
4.6
3
-
10
+100
42
-
-
-
-
-
-
V
m
m
V
S
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
2800 4500
615
190
1.6
-
-
3.2
Source-Drain Diode
Symbol
V
SD
t
rr
Q
rr
Parameter
Forward On Voltage
2
Reverse Recovery Time
Reverse Recovery Charge
Test Conditions
I
S
=20A, V
GS
=0V
I
S
=10A,
V
GS
=0
V
,
dI/dt=100A/µs
Min.
-
-
-
Typ.
-
41
49
Max. Units
1.2
-
-
V
ns
nC
Notes:
1.Pulse width limited by Max. junction temperature
2.Pulse test
3.Surface mounted on 1 in copper pad of FR4 board, t <10sec, 60 C/W at steady state.
4.Starting T
j
=25 C, V
DD
=25V, L=0.1mH, R
G
=25Ω, I
AS
=24A.
o
2
o
THIS PRODUCT IS SENSITIVE TO ELECTROSTATIC DISCHARGE, PLEASE HANDLE WITH CAUTION.
USE OF THIS PRODUCT AS A CRITICAL COMPONENT IN LIFE SUPPORT OR OTHER SIMILAR SYSTEMS IS NOT AUTHORIZED.
APEC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED
HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
APEC RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN.
2
AP2RA04GMT-HF
300
120
T
C
=25 C
250
o
I
D
, Drain Current (A)
200
I
D
, Drain Current (A)
10V
7.0V
6.0V
5.0V
V
G
= 4.0 V
T
C
=150 C
100
o
10V
7.0V
6.0V
5.0V
V
G
=4.0V
80
150
60
100
40
50
20
0
0.0
1.0
2.0
3.0
4.0
0
0.0
1.0
2.0
3.0
4.0
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
4
2.0
I
D
=20A
T
C
=25 C
3.6
o
I
D
=20A
V
G
=10V
Normalized R
DS(ON)
1.6
R
DS(ON)
(m
Ω
)
3.2
1.2
2.8
0.8
2.4
2
2
4
6
8
10
0.4
-50
0
50
100
150
V
GS
, Gate-to-Source Voltage (V)
T
j
, Junction Temperature ( C)
o
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
1.6
30
1.2
20
I
S
(A)
T
j
=150 C
o
T
j
=25 C
o
Normalized V
GS(th)
1.2
0.8
10
0.4
0
0
0.2
0.4
0.6
0.8
1
0.0
-50
0
50
100
150
V
SD
, Source-to-Drain Voltage (V)
T
j
, Junction Temperature ( C)
o
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
3
AP2RA04GMT-HF
10
4000
f=1.0MHz
V
GS
, Gate to Source Voltage (V)
I
D
=20A
V
DS
=20V
8
3000
C
iss
6
C (pF)
2000
4
1000
2
C
oss
C
rss
0
0
10
20
30
40
50
60
0
1
5
9
13
17
21
25
29
Q
G
, Total Gate Charge (nC)
V
DS
,Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1000
1
Duty factor = 0.5
100
Operation in this
area limited by
R
DS(ON)
100us
Normalized Thermal Response (R
thjc
)
0.2
I
D
(A)
0.1
0.1
1ms
10
0.05
P
DM
10ms
T
C
=25
o
C
Single Pulse
100ms
DC
1
10
100
t
T
0.02
Duty factor = t/T
Peak T
j
= PDM x R
thjc
+ T
c
0.01
Single Pulse
1
0.01
0.1
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
V
DS
,Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
V
DS
90%
V
G
Q
G
4.5V
Q
GS
Q
GD
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
4
AP2RA04GMT-HF
MARKING INFORMATION
Part Number
meet Rohs requirement
for low voltage MOSFET only
Package Code : MT
2RA04GMT
YWWSSS
Date Code (YWWSSS)
Y：Last Digit Of The Year
WW：Week
SSS：Sequence
5
