Advanced v0.6
PLUS
™
ProASIC
Fe a t ur es an d B e ne f i ts
High C apaci t y
Family Flash FPGAs
I/O
• 150,000 to 1 million System Gates
• 36k to 198 kbits of Two-Port SRAM
• 106 to 712 User I/Os
P erf orm a nce
• 3.3V, 32-bit PCI (up to 50 MHz)
• Internal System Performance up to 350 MHz
• External System Performance up to 150 MHz
Rep ro gra m m able Fl as h T ech nol ogy
• Schmitt Trigger option on Every Input
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• Bidirectional Global I/Os
• Compliance with PCI Specification Revision 2.2
• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
• Pin Compatible Packages across ProASIC
PLUS
Family
Uni que Cl ock Con dit io ning C ir cui tr y
•
•
•
•
0.22
µ 4
LM Flash-based CMOS Process
Live at Power Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design During Power-Down/
Power-Up Cycles
• Two Integrated PLLs (1.5 to 240 MHz Input and Output
Ranges)
• PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs
S ta ndar d FP GA and AS IC De si gn F low
S ecur e Pr og ram m i ng
• The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
Low P ower
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient, Configurable (Combinatorial or
Sequential) Logic Cells
H ig h P er f o r m ance R ou t ing H i e ra rc hy
• Flexibility with Choice of Industry-Standard Front-End
Tools
• Efficient Design through Front-End Timing and Gate
Optimization
IS P S uppo rt
• In-System Programming (ISP) via JTAG Port
S RA Ms and FIFO s
•
•
•
•
Ultra Fast Local and Long Line Network
High Speed Very Long Line Network
High Performance, Low Skew, Splitable Global Network
100% Routability and Utilization
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
208
456
144, 256
APA300
300,000
8,192
72k
32
2
2
4
32
304
Yes
Yes
208
456
144, 256
• Netlist Generation Ensures Optimal Usage of Embedded
Memory Blocks
• Synchronous and Asynchronous Operation of 24 RAM and
FIFO Configurations (Up to 150 MHz)
Pr oA S I C
PL U S
P r o du ct Pr o f i l e
Device
Maximum System Gates
Maximum Registers
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG
PCI
Package
(by pin count)
PQFP
PBGA
FBGA
April 2002
APA450
450,000
12,288
108k
48
2
2
4
48
356
Yes
Yes
208
456
144, 256
APA600
600,000
21,504
126k
56
2
2
4
56
456
Yes
Yes
208
456
256, 676
APA750
750,000
32,768
144k
64
2
2
4
64
642
Yes
Yes
208
456
676, 896
APA1000
1,000,000
56,320
198k
88
2
2
4
88
712
Yes
Yes
208
456
896, 1152
1
© 2002 Actel Corporation
Pr o A S I C
P L U S
F a m ily F la s h F P GA s
G en er al D e sc r i p t i on
The ProASICPLUS family of devices offers enhanced
performance over Actel’s ProASIC family. It combines the
advantages of ASICs with the benefits of programmable
devices through nonvolatile Flash technology. This enables
engineers to create high-density systems using existing ASIC
or FPGA design flows and tools. In addition, the
ProASICPLUS family offers a unique clock conditioning
circuit based on two on-board phase lock loops (PLLs). The
family offers up to 1 million system gates, supported with up
to 198 kbits of 2-port SRAM and up to 712 user I/Os, all
providing 50 MHz PCI performance.
Advantages to the designer extend beyond performance.
Four levels of routing hierarchy simplify routing, while the
use of Flash technology allows all functionality to be live at
power up, unlike SRAM-based FPGAs. No external Boot
PROM is required to support device programming. While
on-board security mechanisms prevent all access to the
program information, reprogramming can be performed
in-system to support future design iterations and field
upgrades. The device’s architecture mitigates the
complexity of ASIC migration at higher user volume. This
makes ProASICPLUS a cost-effective solution for
applications in the networking, communications,
computing, and avionics markets.
The ProASICPLUS family achieves its nonvolatility and
reprogrammability through an advanced Flash-based 0.22m
LVCMOS process with four-layer metal. Standard CMOS
design techniques are used to implement logic and control
functions, including the PLLs and LVPECL inputs. The
result is predictable performance fully compatible with gate
arrays.
The ProASICPLUS architecture provides
granularity
comparable to gate arrays. The device core consists of a
Sea-of-TilesTM. Each tile can be configured as a flip-flop,
latch, or 3-input/1-output logic function by programming the
appropriate Flash switches. The combination of fine
granularity, flexible routing resources, and abundant Flash
switches allow 100% utilization and over 95% routability for
highly congested designs. Tiles and larger functions are
interconnected through a 4-level routing hierarchy.
Embedded 2-port SRAM blocks with built-in FIFO/RAM
control logic can have user-defined depth and width. Users
can also select programming for synchronous or
asynchronous operation, as well as parity generations or
checking.
The clock conditioning circuitry is unique. Devices contain
two clock conditioning blocks, each with a PLL core, delay
lines, phase shifts (0×, 90×, 180×, 270×), and clock
multipliers/dividers. In short, this is all the circuitry needed
to provide bidirectional access to the PLL, and operation up
to 240 MHz. The PLL block contains four programmable
frequency dividers which allow the incoming clock signal to
be divided by a wide range of factors from 1 to 64. The clock
conditioning circuit also delays or advances the incoming
reference clock up to 4ns (in increments of 0.25ns). The
PLL can be configured internally or externally during
operation without redesigning or reprogramming the part.
In addition to the PLL, there are two LVPECL differential
input pairs to accommodate high speed clock and data
inputs.
To support customers’ needs for more comprehensive, lower
cost board-level testing, Actel’s ProASIC
PLUS
devices are
fully compatible with IEEE Standard 1149.1 for test access
port and boundary-scan test architecture. For more details
on the Flash FPGA implementation please refer to the
“Boundary Scan” section on page 12.
ProASIC
PLUS
devices are available in a variety of
high-performance plastic packages. Those packages, and the
performance features discussed above, are described in
more detail in the following sections of this document:
•
“Features and Benefits” section on page 1
•
“ProASICPLUS Architecture” section on page 5
•
“Routing Resources” section on page 6
•
“Clock Trees” section on page 9
•
“Input/Output Blocks” section on page 10
•
“LVPECL Input Pads” section on page 11
•
“Boundary Scan” section on page 12
•
“User Security” section on page 14
•
“Embedded Memory Floorplan” section on page 14
•
“Design Environment” section on page 17
•
“Package Thermal Characteristics” section on page 19
•
“Operating Conditions” section on page 22
•
“DC Electrical Specifications (V
DDP
= 2.5V +/-0.2V)”
section on page 23
–
page 25
•
“AC Specifications (3.3V PCI Revision 2.2 Operation)”
section on page 26
•
“Clock Conditioning Circuit” section on page 27
•
“Embedded Memory Specifications” section on page 35
•
“Package Pin Assignments” section on page 55
–
page 109
• For more information concerning In-System Programming
with ProASIC
PLUS
, refer to the application note,
Performing Internal In-System Programming Using
Actel’s ProASIC
PLUS
Devices.
http://www.actel.com/appnotes/PAplusISPAN.pdf
2
Advanced v0.6
Pr o A SI C
P L U S
F a m ily F la s h F P GA s
O r d e r i n g I nf o r m a t i o n
_
APA1000
FG
1152
ES
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
PQ = Plastic Quad Flat Pack
FG = FineBall Grid Array
PB = Plastic Ball Grid Array
Speed Grade
Blank = Standard Speed
1 = TBD
Part Number
APA150
APA300
APA450
APA600
APA750
APA1000
=
=
=
=
=
=
150,000 Equivalent System Gates
300,000 Equivalent System Gates
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
1,000,000 Equivalent System Gates
Pr od uc t P l a n
Speed Grade
Std
APA150 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA300 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA450 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA600 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
256-Pin Fine Ball Grid Array (FBGA)
676-Pin Fine Ball Grid Array (FBGA)
APA750 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Fine Ball Grid Array (PBGA)
676-Pin Fine Ball Grid Array (FBGA)
896-Pin Plastic Ball Grid Array (FBGA)
APA1000 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
896-Pin Plastic Ball Grid Array (FBGA)
1152-Pin Plastic Ball Grid Array (FBGA)
Applications:
C = Commercial
I = Industrial
Availability:
Application
–1
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
C
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
✔
✔
P
P
✔
✔
P
P
P
= Planned
✔
= Limited Availability – Contact your Actel Sales representative for the latest availability
information.
Advanced v0.6
3
Pr o A S I C
P L U S
F a m ily F la s h F P GA s
Pl a s t i c D e vi c e Re so u r ce s
User I/Os
Device
APA150
APA300
APA450
APA600
APA750
APA1000
PQFP
208-Pin
158
158
158
158
158
158
PBGA
456-Pin
242
290
344
356
356
356
FBGA
144-Pin
100
100
100
FBGA
256-Pin
186
186
186
186
454
454
562
642
712
FBGA
676-Pin
FBGA
896-Pin
FBGA
1152-Pin
Package Definitions
PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array
4
Advanced v0.6
Pr o A SI C
P L U S
F a m ily F la s h F P GA s
Pr oA S I C
PL U S
A r c hi t e c t u r e
Fla sh S wit ch
The proprietary ProASIC
architecture provides
granularity comparable to gate arrays.
The ProASIC
PLUS
device core (Figure
1)
consists of a
Sea-of-Tiles
™
. Each tile can be configured as a 3-input logic
function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
the
appropriate
Flash
switch
interconnections (Figure
2 on page 6
and
Figure 3 on
page 6).
Tiles and larger functions are connected with any
of the four levels of routing hierarchy. Flash cells are
distributed throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Flash switches
are programmed to connect signal lines to the appropriate
logic cell inputs and outputs. Dedicated high-performance
lines are connected as needed for fast, low-skew global
signal distribution throughout the core. Maximum core
utilization is possible for virtually any design.
ProASIC
PLUS
devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking.
Table 3 on
page 14
lists the 24 basic memory configurations.
PLUS
Unlike SRAM FPGAs, ProASIC
PLUS
uses a live on
power-up ISP Flash switch as its programming element.
In the
ProASIC
PLUS
Flash switch,
two transistors share the
floating gate, which stores the programming information.
One is the sensing transistor, which is only used for writing
and verification of the floating gate voltage. The other is the
switching transistor. It can be used in the architecture to
connect/separate routing nets or to configure logic. It is also
used to erase the floating gate (Figure
2 on page 6).
Logi c Ti le
The logic tile cell (Figure
3 on page 6)
has three inputs (any
or all of which can be inverted) and one output (which can
connect to both ultra fast local and efficient long line
routing resources). Any three-input one-output logic
function, except a three input XOR, can be configured as
one tile. The tile can be configured as a latch with clear or
set or as a flip-flop with clear or set. Thus the tiles can
flexibly map logic and sequential gates of a design.
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
Figure 1 •
The ProASIC
PLUS
Device Architecture
Advanced v0.6
5
