v3.5
ProASIC
PLUS
Flash Family FPGAs
Features and Benefits
High Capacity
•
•
•
•
•
•
•
•
•
•
•
75,000 to 1 Million System Gates
27k to 198kbits of Two-Port SRAM
66 to 712 User I/Os
0.22µ
4LM
Flash-Based CMOS Process
Live at Power-Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
3.3V, 32-Bit PCI (up to 50 MHz)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
™
)
Prevents Read Back of Programming Bitstream
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
Ultra-Fast Local and Long-Line Network
High Speed Very Long-Line Network
APA075
75,000
3,072
27k
12
2
2
4
24
158
Yes
Yes
100, 144
208
–
144
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
100
208
456
144, 256
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
TM
I/O
Schmitt-Trigger Option on Every Input
2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across the ProASIC
PLUS
Family
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Frontend Timing and Gate Optimization
In-System Programming (ISP) via JTAG Port
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Performance
Secure Programming
Low Power
•
•
•
Standard FPGA and ASIC Design Flow
ISP Support
SRAMs and FIFOs
High Performance Routing Hierarchy
•
•
Table 1 •
ProASIC
PLUS
Product Profile
Device
Maximum System Gates
Maximum Tiles (Registers)
Embedded RAM Bits
(k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package
(by pin count)
TQFP
PQFP
PBGA
FBGA
APA300
300,000
8,192
72k
32
2
2
4
32
290
Yes
Yes
–
208
456
144, 256
APA450
450,000
12,288
108k
48
2
2
4
48
344
Yes
Yes
–
208
456
APA600
600,000
21,504
126k
56
2
2
4
56
454
Yes
Yes
–
208
456
APA750
750,000
32,768
144k
64
2
2
4
64
562
Yes
Yes
–
208
456
676, 896
APA1000
1,000,000
56,320
198k
88
2
2
4
88
712
Yes
Yes
–
208
456
896, 1152
144, 256, 484 256, 484, 676
April 2004
© 2004 Actel Corporation
i
ProASIC
PLUS
Flash Family FPGAs
Ordering Information
APA1000
_
F
FG
1152
I
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
TQ = Thin Quad Flat Pack (0.5mm pitch)
PQ = Plastic Quad Flat Pack (0.5mm pitch)
FG = Fine Pitch Ball Grid Array (1.0mm pitch)
BG = Plastic Ball Grid Array (1.27mm pitch)
Speed Grade
Blank = Standard Speed
F = 20% Slower than Standard
Part Number
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
=
=
=
=
=
=
=
75,000 Equivalent System Gates
150,000 Equivalent System Gates
300,000 Equivalent System Gates
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
1,000,000 Equivalent System Gates
Plastic Device Resources
User I/Os*
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
TQFP
100-Pin
66
66
TQFP
144-Pin
107
PQFP
208-Pin
158
158
158
158
158
158
158
242
290
344
356
356
356
PBGA
456-Pin
FBGA
144-Pin
100
100
100
100
186
186
186
186
344
370
454
454
562
642
712
FBGA
256-Pin
FBGA
484-Pin
FBGA
676-Pin
FBGA
896-Pin
FBGA
1152-Pin
Package Definitions
TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array
*Each pair of PECL I/Os were counted as one user I/O.
General Guideline
Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee
performance beyond the limits specified within the datasheet.
ii
v3.5
ProASIC
PLUS
Flash Family FPGAs
Temperature Grade Offerings
Package
TQ100
TQ144
PQ208
BG456
FG144
FG256
FG484
FG676
FG896
FG1152
C, I
APA075
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
APA150
C, I
APA300
APA450
APA600
APA750
APA1000
Speed Grade and Temperature Matrix
-F
C
I
X
Std
X
X
v3.5
iii
ProASIC
PLUS
Flash Family FPGAs
Table of Contents
General Description
ProASIC
PLUS
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-25
1-26
1-27
1-28
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63
Recommended Design Practice for V
PN
/V
PP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64
Package Pin Assignments
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
v3.5
v
