APA4838
Stereo 2.8W Audio Power Amplifier with DC Volume Control
and Selectable Gain
Features
•
•
•
•
•
•
•
Operating Voltage : 4.5V to 5V
Stereo switchable bridged/single-ended
power amplifiers
DC Volume Control Interface , 0dB to –78dB
with precision scale
Supply Current , I
DD
= 15mA at Stereo BTL
Low Shutdown Current , I
DD
= 0.7µA
Bridge-Tied Load (BTL) or Single-Ended-(SE)
Modes Operation
Output Power at 1% THD+N , V
DD
=5V
General Description
The APA4838 is a monolithic integrated circuit , which
provides DC volume control , and a stereo bridged
audio power amplifiers capable of producing 2.8W
(2.3W) into 3Ω with less than 10% (1.0%) THD+N.
APA4838 includes a DC volume control , stereo
bridge-tied and single-ended audio power amplifiers
, stereo docking outputs , and a selectable gain con-
trol , that makes it optimally fittable for notebook PC
, multimedia monitors , and other portable
applications. The attenuator range of the volume
control in APA4838 is from 0dB (DC_Vol=0.8V
DD
) to
–78dB (DC_Vol=0V) with 31 steps. Both of the depop
circuitry and the thermal shutdown protection circuitry
are integrated in APA4838 , that reduces pops and
clicks noise during power up or shutdown mode op-
eration , and protects the chip from being destroyed
by over temperature failure. To simplify the audio
system design , APA4838 combines a stereo bridge-
tied loads (BTL) mode for speaker drive and a stereo
single-end (SE) mode for headphone drive into a
single chip , where both modes are easily switched
by the HP Sense input control pin signal. Besides
the low supply current design to increase the effi-
ciency of the amplifiers , APA4838 also features a
shutdown function which keeps the supply current
only 0.7µA (typ).
•
–
2.3W/Ch (typ) into a 3
Ω
Load
–
2.0W/Ch (typ) into a 4
Ω
Load
–
1.2W/Ch (typ) into a 8
Ω
Load
Output Power at 10% THD+N , V
DD
=5V
–
2.8W/Ch (typ) into a 3
Ω
Load
–
2.3W/Ch (typ) into a 4
Ω
Load
–
1.5W/Ch (typ) into a 8Ω Load
•
•
•
•
•
•
Single-ended mode at 1.0% THD+N
–
95mW/Ch (typ) into 32Ω Load
Depop Circuitry Integrated
Thermal shutdown protection and over current
protection circuitry
High supply voltage ripple rejection
PC99 Compliant
28-pin TSSOP-P (with enhanced thermal pad)
power package available
Pin Description
GN D
Shutdown
G ain Select
M ode
M ute
V
DD
DC V ol
GN D
Right Dock
Right In
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Right O ut +
V
DD
Right O ut -
Right G ain 2
Right G ain 1
GN D
BY PA SS
HP Sense
GN D
Left G ain 1
Left G ain 2
Left O ut -
V
DD
Left O ut +
Applications
•
•
•
Notebook and Desktop Computers
Multimedia Monitors
Portable Applications
Beep In
Left In
Left Dock
GN D
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
ANPEC Electronics Corp.
Rev. A.1
-
Apr., 2003
1
www.anpec.com.tw
APA4838
Ordering and Marking Information
APA4838
H a n d lin g C o d e
T em p. R an g e
P ac ka ge C od e
P ackage C ode
R : T S S O P -P
Tem p. R ange
I : -4 0 to 8 5
°
C
H a n d lin g C o d e
TU : Tube
TR : Tape & R eel
A P A 4838 R :
A P A 4838
XXXXX
X X X X X - D a te C o d e
Block Diagram
Gain Select
20K
Ω
20K
Ω
Left Gain1
Mode
Mute
HP Sense
DC_Vol
Left Dock
20K
Ω
Left
Audio Input
200K
Ω
200K
Ω
Right
Audio Input 20K
Ω
20K
Ω
Mode
Control
Left Gain2
20K
Ω
10K
Ω
0.068
µ
F
10K
Ω
- Left Out
+
-
Bias
-
+
Bias
-
+
+ Right Out
20K
Ω
-
+
Power
Management
10K
Ω
10K
Ω
20K
Ω
Right Gain1
Right Gain2
Click and Pop
Suppression
Circuitry
20K
Ω
2
0.33
µ
F
Beep In
0.33
µ
F
Right In
Right Dock
20K
Ω
Shutdown
V
DD
GND
Beep
Detect
Bypass
Copyright
ANPEC Electronics Corp.
Rev. A.1
-
Apr., 2003
+
-
+
-
Volume
Control
31 steps
Left In
20K
Ω
20K
Ω
+ Left Out
20K
Ω
- Right Out
0.068
µ
F
20K
Ω
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APA4838
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
V
DD
V
IN
T
A
T
J
T
STG
T
S
V
ESD
P
D
Parameter
Rating
-0.3 to 6
Unit
V
V
°C
°C
°
C
°C
V
W
Supply Voltage
Input Voltage Range, HP sense, Shutdown,
-0.3 to V
DD
+0.3
Mute, Mode, Gain Select
Operating Ambient Temperature Range
-40 to 85
Maximum Junction Temperature
Internally Limited*
1
Storage Temperature Range
-65 to +150
Soldering Temperature,10 seconds
260
Electrostatic Discharge
-2000 to 2000*
2
Power Dissipation
Internally Limited
Note:
1.APA4838 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Recommended Operating Conditions
Min.
Supply Voltage, V
DD
High level threshold voltage, V
IH
Low level threshold voltage, V
IL
Common mode input voltage, V
ICM
Shutdown, Mute, Mode, Gain Select
HP Sense
Shutdown, Mute, Mode, Gain Select
HP Sense
V
DD
-1.0
4.5
2
4
1.0
3
Max.
5.5
Unit
V
V
V
V
Thermal Characteristics
Symbol
R
THJA
Parameter
Thermal Resistance from Junction to Ambient in Free Air
TSSOP-P*
45
K/W
Value
Unit
* 5 in
2
printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias.
The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Copyright
ANPEC Electronics Corp.
Rev. A.1
-
Apr., 2003
3
www.anpec.com.tw
APA4838
Electrical Characteristics
Electrical Characteristics for Entire IC
The following specifications apply for V
DD
= 5V unless otherwise noted. Limits apply for T
A
= 25°C
Symbol
V
DD
I
DD
I
SD
Parameter
Supply Voltage
Quiescent Power Supply
Current
Shutdown Current
Test Conditions
Min.
4.5
APA4838
Typ.
Max.
5.5
15
0.7
25
2.0
Unit
V
mA
µA
V
IN
=0V, I
O
=0A
V
PIN 2
= V
DD
Electrical Characteristics for Volume Attenuators
The following specifications apply for V
DD
= 5V. Limits apply for T
A
= 25°C
Symbol
C
RANGE
A
M
Parameter
Attenuator Range
Mute Attenuation
Test Conditions
Gain with V
PIN 7
=5V
Attenuation with V
PIN 7
=0V
V
PIN 5
=5V, Bridged Mode
V
PIN 5
=5V, Single-Ended Mode
APA4838
Min.
Typ. Max.
±0.5
-65
-78
-70
-70
Unit
dB
dB
Electrical Characteristics for BTL Mode Operation
The following specifications apply for V
DD
= 5V unless otherwise noted. Limits apply for T
A
= 25°C
Symbol
V
OS
P
O
Parameter
Output Offset Voltage
Output Power
Test Conditions
THD+N
PSRR
X
TALK
SNR
V
N
V
IN
=0V
THD=1%, f=1kHz
R
L
=3Ω
R
L
=4Ω
R
L
=8Ω
THD=10%, f=1kHz
R
L
=8Ω
Total Harmonic Distortion + Noise A
VD
=2, f=1kHz
R
L
=4Ω , P
O
=1.5W
R
L
=8Ω , P
O
=1W
V
RIPPLE
=100mV
Rms
C
B
=2.2µF,
Power Supply Rejection Ratio
R
L
=8Ω, f=1kHz
C
B
=2.2µF, f=1kHz, R
L
=8Ω
Channel Separation
V
DD
=5V, P
O
=1.1W, R
L
=8Ω,A-Wtd
Signal-to-Noise Ratio
Filter
R
L
=8Ω,A-Wtd Filter
Output Noise Voltage
APA4838
Typ.
5
2.3
2.0
1.2
1.5
0.07
0.07
70
90
95
30
Unit
mV
W
%
dB
dB
dB
µV
Copyright
ANPEC Electronics Corp.
Rev. A.1
-
Apr., 2003
4
www.anpec.com.tw
APA4838
Electrical Characteristics (Cont.)
Electrical Characteristics for SE Mode Operation (Cont.)
The following specifications apply for V
DD
= 5V unless otherwise noted. Limits apply for T
A
= 25°C
Symbol
V
OS
P
O
THD+N
PSRR
X
TALK
SNR
V
N
Parameter
Output Offset Voltage
Output Power
V
IN
=0V
THD=1%,
THD=10%,
Test Conditions
f=1kHz, R
L
=32Ω
f=1kHz, R
L
=32Ω
APA4838
Typ.
5
95
110
0.05
0.07
52
90
102
20
Unit
mV
mW
%
%
dB
dB
dB
µV
Total Harmonic Distortion A
V
= 1 , V
OUT
=1V
RMS
, R
L
=10kΩ, f=1kHz
plus Noise
P
O
=75mW, R
L
=32Ω, A
V
= 1, f=1kHz
Power Supply Rejection
V
RIPPLE
=100mV
RMS
, f=120Hz, C
B
=2.2µF
Ratio
Channel Separation
C
B
=2.2µF, R
L
=8Ω , f=1kHz
Signal-to-Noise Ratio
P
O
=75mW, R
L
=32Ω, A-Wtd Filter
Output Noise Voltage
R
L
=32Ω, A-Wtd Filter
Pin Description
Pin
Name
GND
Shutdown
Gain Select
Mode
Mute
V
DD
DC_Vol
Right Dock
Right In
Beep In
Left In
Left Dock
Left Out +
Left Out -
Left Gain 2
Left Gain 1
HP Sense
No
1, 8, 14,
20, 23
2
3
4
5
6, 16, 27
7
9
10
11
12
13
15
17
18
19
21
I/O
Ground connection for circuitry.
I Shutdown mode control signal input, place entire IC in shutdown mode when
held high, Idd=0.7uA
I Gain select input pin, logic high will switch the amplifier to external gain
mode, and logic low will switch to internal unity gain.
I Mode select input pin, fixed gain when logic L and gain adjustable mode
when logic H.
I Mute control input pin, active H.
Supply voltage input pin
I Volume control function input pin.
O Right docking output pin
I Right channel audio input pin
I Beep signal input pin
I Left channel audio input pin
O Right docking output pin
O Left channel positive output pin
O Left channel negative output pin
Connect pin 2 of the external gain setting resistor for left channel
Connect pin 1 of the external gain setting resistor for left channel
I Headphone sense control pin
5
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Description
Copyright
ANPEC Electronics Corp.
Rev. A.1
-
Apr., 2003
FPGA/CPLD
