A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: September 1, 2016
Recommended Substitutions:
no direct replacement
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Features and Benefits
• High efficiency integrated FETs optimized for lower duty
cycle voltage conversion: 27 mΩ high side, 12 mΩ low side
• Power input voltage range: 3 to 16 V
• Control input voltage range: 4.5 to 16V
• djustable output voltage, down to 0.6 V
A
• 5 V LDO Regulator
• Extremely short minimum controllable on-time;
example: allows 12 V conversion to 0.6 V at >1 MHz
• Reference accuracy of ±1% throughout temperature range
¯ ¯¯¯
•
¯ ¯ ¯ ¯ ¯ and Power OK pins for operating and
FAULT
protection modes
• Low power mode (LPM) or fixed continuous conduction
mode (FCCM) operation
• Programmable soft-start / hiccup shutdown period
• Ultra-fast transient response
Description
The A8672 is a synchronous buck converter capable of
delivering up to 8 A. The A8672 utilizes valley current mode
control, allowing very short on-times to be achieved. This makes
it ideal for applications that require very low output voltages
relative to the input voltage, combined with high switching
frequencies. Valley current mode control inherently provides
improved transient response over traditional switcher schemes,
through the use of a voltage feedforward loop and frequency
modulation during large signal load changes.
The A8672 includes a comprehensive set of diagnostic flags,
allowing the host platform to react to a myriad of different
conditions. A fault output indicates when either the temp-
erature is becoming unusually high, or a single point failure
has occurred; for example, the switching node (LX) shorted to
ground, or the timing resistor going open-circuit. A Power OK
(POK) output is also provided after a fixed delay, to indicate
when the output voltage is within regulation. The selectable
pulse-by-pulse current limit avoids the requirement to oversize
the inductor to cope with large fault currents.
The device package (EG) is a 28-contact, 4 mm × 5 mm,
0.75 mm nominal overall height QFN with exposed thermal
pad. The package is lead (Pb) free, with 100% matte tin
leadframe plating.
Applications
• Servers
• Point of load supplies
• Network and telecom
• Storage
Package: 28-contact QFN with exposed
thermal pad (suffix EG)
Approximate size
Typical Application Diagram
V
IN
12 V
C1
22 µF
C2
22 µF
C3
22 µF
C4
22 µF
R1
90.9kΩ
C5
47 nF
VIN
BOOT
LX
L1
1 µH
C6
100 µF
C7
100 µF
VOUT
1.2 V
TON
VDD
VREG
BIAS
MODE
EN
A8672
FB
ILIM
PAD
COMP
R6
10 kΩ
R7
10 kΩ
C8
2.2 µF
C9
470 nF
V
pull-up
R2
20 kΩ
R3
20 kΩ
R4
249 k
Ω
R5
56 k
Ω
C12
22 pF
FAULT
POK
C10
10 nF
FAULT
POK
SS
AGND
PGND
C11
680 pF
V
IN
= 12 V, V
OUT
= 1.2 V, and f
SW
= 500 kHz
A8672-DS, Rev. 3
MCO-0000466
July 5, 2018
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Selection Guide
A8672EEGTR-T
7000 pieces per 13-inch reel
™
for additional packing options
*Contact Allegro
Part Number
Packing*
Absolute Maximum Ratings
Characteristic
VIN, VDD, TON, VREG, BIAS and EN
Pin Voltage
LX Pin Voltage
BOOT Pin Voltage
All Other Pins
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Symbol
V
I
V
LX
V
BOOT
–
T
A
T
J
(max)
T
stg
E temperature range
With respect to GND
With respect to GND
t < 50 ns, with respect to GND
With respect to GND
Notes
Rating
–0.3 to 18
–0.6 to V
IN
+ 0.3
–2.0
V
LX
– 0.3 to
V
LX
+ 8.0
–0.3 to 7.0
–40 to 85
150
–55 to 150
Unit
V
V
V
V
V
ºC
ºC
ºC
Table of Contents
Specifications
Thermal Characteristics
Functional Block Diagram
Pin-out Diagram and Terminal List
Electrical Characteristics
Basic Operation
Output Voltage Selection
Switch On-Time and Switching Frequency
Valley Current Limit
Inductor Selection
2
3
3
4
5
7
7
7
8
8
Functional Description
7
Output Capacitor Selection
Input Capacitor Selection
Soft-Start and Output Overloads
Fault Handling and Reporting
Control Loop
Control Loop Design Approach
Thermal Considerations
Regulator Efficiency
9
9
10
12
14
15
18
19
Layout
Package Outline Drawing
20
21
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Functional Block Diagram
VDD
5V LDO
Regulator
Bias
Regulator
Enable
Driver
TON
On
Timer
Off
Timer
ILIM
MODE
Hiccup
BIAS
BOOT VIN
EN
VREG
LX
Control
Logic
Driver
BIAS
-
Current
Amplifier
+
-
+
-
+
Offset
VDD UVLO
FB OV
FB UV
TOT
TSD
POK
FAULT
Fault
Reporting
and
Shutdown
+
Regulator
Comparator
PGND
OV Ref
FB OV
-
Overvoltage
Comparator
FB
FB UV
+
-
g
m
Amplifier
UV Ref
Ref
FB
Hiccup
Soft Start
and Hiccup
Period
0.6 V
Ref
Undervoltage
Comparator
PAD
COMP
SS
AGND
Thermal Characteristics
may require derating at maximum conditions, see application information
Characteristic
Symbol
R
θJA
R
θJP
Test Conditions*
Value
33
2
Unit
ºC/W
ºC/W
Package Thermal Resistance (Junction to Ambient)
Package Thermal Resistance (Junction to Pad)
Estimated, on 4-layer PCB based on JEDEC
standard
*Additional thermal information available on the Allegro website
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
27 COMP
24 MODE
23 BIAS
22 LX
21 LX
20 LX
PAD
19 LX
18 LX
17 LX
16 LX
15 BOOT
TON 10
FAULT 12
POK 13
VREG 11
EN 14
9
25 ILIM
26 SS
28 FB
AGND
PGND
PGND
1
2
3
4
5
6
7
8
Pin-out Diagram
PGND
PGND
PGND
VIN
VIN
Terminal List Table
Number
1
2,3,4,5,6
7,8
9
10
11
12
13
14
15
16,17,18,19,
20,21,22
23
24
25
26
27
28
Name
AGND
PGND
VIN
VDD
TON
VREG
¯ ¯¯¯ ¯
¯ L¯
¯
FAU¯ T
POK
EN
BOOT
LX
BIAS
MODE
ILIM
SS
COMP
FB
VDD
Function
Analog ground. Connect to PGND at PAD of device. This pin should be used as the FB resistor divider
ground reference for optimal accuracy (see Typical Applications section circuit diagrams).
Power ground. Connect to PAD of device.
Power input to the drain of the internal high-side MOSFET. This pin must be locally bypassed (see Typical
Applications section circuit diagrams).
Power input for the control circuit and drive signals for the internal switching MOSFETs. This pin can be
either connected directly to VIN, or in applications where a low VIN voltage is used, it can be driven by a
separate power source to ensure adequate overdrive of the switching MOSFETs and control supply.
On-Time pin. The resistor connected between this pin and VIN defines the on-time of the regulator. This in
turn defines the switching frequency for a given output voltage.
5 V LDO regulator output and supply for internal control circuitry.
¯ L¯
¯
Open drain ¯ ¯¯¯ ¯ output. This pin is logic low if the on-time exceeds a certain value, if the LX node is
FAU¯ T
shorted to ground, or if the thermal shutdown threshold (T
J
> 140°C) has been reached (see Fault Handling
and Reporting table).
Open drain Power Okay (power good) output. This pin is logic low if any fault (as defined in the Fault
Handling and Reporting table) occurs, other than an overtemperature condition (T
J
> 140°C).
Enable pin. This pin is a logic input that turns the converter on or off. When EN > V
ENHI
, the part turns on.
High-side gate drive supply input. This pin supplies the drive for the high-side switching MOSFET switch.
The source of the internal high-side switching MOSFET. The output inductor and BOOT capacitor should be
connected to this pin (see Typical Applications section circuit diagrams).
Internal regulated bias supply for the control circuit and drives for switching MOSFETs (see Typical
Applications section circuit diagrams for recommended capacitors).
When pulled to the VREG supply via a 10 kΩ resistor, fixed continuous conduction mode (FCCM) is
maintained across the full load range. When pulled directly to GND, the switcher enters lower power mode
(LPM) at light loads.
Valley current limit setting. Connect a resistor to ground to set a voltage between 2.75 and 1.5 V that
corresponds to a valley overload current of between 9 and 3 A (typ).
Soft-start ramp pin. The capacitor connected to this pin defines the rate of rise of the output voltage and
the effective inrush current. Soft-start also defines the hiccup shutdown period with either an overload or
overvoltage condition.
Output of the error amplifier and compensation node. Connect a series R-C network from this pin to GND for
control loop regulation.
Feedback input pin of the error amplifier. Connect a resistor divider from the converter output voltage node,
VOUT, to this pin to set the converter output voltage. This pin is also monitored for both output overvoltage
and undervoltage conditions (see Fault Handling and Reporting table for more details).
Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the
PCB. This pad must be soldered to the PCB for proper operation and should be connected to the ground
plane by through-hole vias (see Layout section for further details).
–
PAD
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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