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SpeedChip XRS7000 and

XRS3000 Series

User Manual

The XRS7004, XRS7003 and XRS3003 are HSR

and PRP (IEC 62439-3 Clause 5 & 4) enabled single-

chip gigabit Ethernet switches. XRS7003 and

XRS3003 can be employed in HSR and PRP End-

nodes and XRS7004 in both End-Nodes and HSR

and PRP RedBoxes. A QuadBox can be built using

two XRS7004 devices.

Features

•

144-pin Plastic Enhanced Quad Flat Pack

(EQFP) (22mm x 22mm, 0.5 mm pitch) or

256-pin Fine Ball Grid Array (FBGA) Package

(17mm x 17mm, 1.0 mm ball pitch)

Industrial Temperature Range

-40

C to +100

Two (XRS7003, XRS3003) or three

(XRS7004) 10/100/1000 Mbit/s Full-

Duplex Ethernet interfaces (RGMII)

10/100 Mbit CPU port (RMII)

Gigabit wire speed forwarding capacity, non-

blocking

I2C and MDIO interfaces for register access

(only MDIO in XRS3003)

Cut-through and Store-and-Forward

operation

Quality of Services (QoS) with four priority

queues per port

Per port packet filtering

VLAN tagging (not in XRS3003)

Priority tagging (not in XRS3003)

IEEE 1588 Precision Time Protocol (PTP)

support with internal Real-Time Clock (RTC)

•

HW counters for implementing Remote

Network MONitoring (RMON) SNMP MIB (not

in XRS3003)

Support for MAC address based

authentication methods

Support for Spanning Tree Protocol (STP)

and Rapid Spanning Tree Protocol (RSTP)

implementations

PPS (Pulse per Second) input and output

(only output in XRS3003)

•

High-availability Seamless Redundancy and

Parallel Redundancy Protocol

HSR and PRP protocols are used in applications that

require short reaction time and high availability.

Typical applications include smart grid electrical

substation automation and other critical networking

applications such as industrial automation, motion

control, vehicle and military communication. HSR and

PRP provide a network that has no single point of

failure and zero recovery time in case of a failure:

Single network faults will not result in any frame loss.

The network is fully operational even during

maintenance as any network device can be

disconnected and replaced without breaking the

network connectivity.

•

XRS7000 and XRS3000 User Manual, Version 1.3

Table 1. Device Features

Feature

10/100/1000 Mbit/s

RGMII ports

10/100 Mbit/s RMII ports

High-Availability Seamless

Redundancy (HSR)

Parallel Redundancy

Protocol (PRP)

Precision Time Protocol

(PTP)

Queues per port

Maximum number of VLANs

XRS7004E

XRS7004F

XRS7003E

XRS7003F

XRS3003F

Yes

MDIO, I

4096

MDIO, I

4096

MDIO, I

4096

MDIO, I

4096

MDIO only

No VLAN

support

Up to 512

hops

1 MAC

Address

FBGA256

-40

C to

+100

Recommended HSR

network size

HSR proxy node table size

Up to 512

hops

512 MAC

Addresses

EQFP144

-40

C to

+100

Up to 512

hops

512 MAC

Addresses

FBGA256

-40

C to

+100

Up to 512

hops

64 MAC

Addresses

EQFP144

-40

C to

+100

Up to 512

hops

64 MAC

Addresses

FBGA256

-40

C to

+100

Package

Operating Junction

Temperature range

XRS7000 and XRS3000 User Manual, Version 1.3

Contents

1. CONVENTIONS USED IN THIS DOCUMENT .................................................................................................................... 8

2. TYPICAL APPLICATIONS .................................................................................................................................................. 9

3. PIN DESCRIPTION ......................................................................................................................................................... 11

3.1

3.2

EQFP144 Package .................................................................................................................................................................................. 11

FBGA256 Package.................................................................................................................................................................................. 19

4. FUNCTIONAL OVERVIEW .............................................................................................................................................. 28

5. REGISTER INTERFACE .................................................................................................................................................. 29

5.1

5.2

5.3

5.4

6.1

Device Identification Registers ............................................................................................................................................................ 29

MDIO Slave ................................................................................................................................................................................................. 30

I2C Slave ..................................................................................................................................................................................................... 32

MDIO and I2C Slave Address Configuration .................................................................................................................................... 37

Inbound Processing ................................................................................................................................................................................ 41

RX MII ......................................................................................................................................................................................... 41

Timestamp ................................................................................................................................................................................ 42

RX Pre-process....................................................................................................................................................................... 42

Forwarding Decision ............................................................................................................................................................. 42

Inbound Policy ......................................................................................................................................................................... 44

Priority-setting ........................................................................................................................................................................ 46

Precision Time Protocol ....................................................................................................................................................... 46

Management Trailer .............................................................................................................................................................. 48

MAC Address Table ............................................................................................................................................................... 49

Virtual LANs (VLANs) ............................................................................................................................................................. 54

Forward Portmask ................................................................................................................................................................. 55

Outbound Processing ............................................................................................................................................................................. 55

TX Post-process ..................................................................................................................................................................... 55

TX MII ......................................................................................................................................................................................... 55

Timestamp ................................................................................................................................................................................ 55

PTP Overwrite ......................................................................................................................................................................... 55

Forwarding Core ...................................................................................................................................................................................... 56

Memory Controller ................................................................................................................................................................. 56

Priority Queues ....................................................................................................................................................................... 56

Frame Early Drop .................................................................................................................................................................... 57

HSR (High-availability Seamless Redundancy) ............................................................................................................................... 58

Forwarding of HSR Frames ................................................................................................................................................. 59

HSR Port Modes ..................................................................................................................................................................... 61

PRP (Parallel Redundancy Protocol) .................................................................................................................................................. 62

Forwarding of PRP Frames ................................................................................................................................................. 62

HSR/PRP interoperability ..................................................................................................................................................................... 64

Allowed Port Modes ................................................................................................................................................................................ 65

Software Reset ......................................................................................................................................................................................... 65

Switch Configuration Registers ........................................................................................................................................................... 66

General Switch Configuration Registers ......................................................................................................................... 67

Frame Timestamp Registers ............................................................................................................................................... 74

Virtual LAN Configuration Registers................................................................................................................................. 80

6. REDUNDANT SWITCH (RS) ........................................................................................................................................... 38

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

XRS7000 and XRS3000 User Manual, Version 1.3

Contents

6.10 Port Configuration Registers ................................................................................................................................................................ 81

General Configuration and State Registers.................................................................................................................... 82

HSR/PRP Registers .............................................................................................................................................................. 86

PTP Registers .......................................................................................................................................................................... 87

Counter Registers .................................................................................................................................................................. 90

Inbound Policy Registers ...................................................................................................................................................103

7. REAL-TIME CLOCK (RTC) ............................................................................................................................................ 107

7.1

8.1

9.1

10.1

10.2

10.3

10.4

Registers...................................................................................................................................................................................................107

Absolute Maximum Ratings ................................................................................................................................................................120

Recommended Operating Conditions .............................................................................................................................................120

Package Thermal Information ............................................................................................................................................................121

DC Electrical Characteristics ..............................................................................................................................................................122

Current consumption ..........................................................................................................................................................122

I/O Characteristics ..............................................................................................................................................................123

8. TIME STAMPER (TS) .................................................................................................................................................... 112

9. GENERAL-PURPOSE IO (GPIO) .................................................................................................................................. 116

10. ELECTRICAL SPECIFICATION ..................................................................................................................................... 120

10.5 Interface Timing......................................................................................................................................................................................123

Input Clock Timing ...............................................................................................................................................................123

Reset Timing ..........................................................................................................................................................................124

RGMII Timing .........................................................................................................................................................................125

RMII Timing ............................................................................................................................................................................126

I2C Timing ..............................................................................................................................................................................128

MDIO Timing ..........................................................................................................................................................................129

11. MECHANICAL SPECIFICATION ................................................................................................................................... 130

11.1 EQFP144 Package ................................................................................................................................................................................130

11.2 FBGA256 Package................................................................................................................................................................................132

12. ORDERING INFORMATION.......................................................................................................................................... 134

12.1 Part Ordering Numbers ........................................................................................................................................................................134

12.2 Sales Offices ............................................................................................................................................................................................134

Figures

Figure 1. End-Node Application......................................................................................................................................................................... 9

Figure 2. RedBox Application ............................................................................................................................................................................. 9

Figure 3. Multiport RedBox Application ........................................................................................................................................................ 10

Figure 4. QuadBox Application ........................................................................................................................................................................ 10

Figure 5. XRS7004E Device Pinout (Top View).......................................................................................................................................... 11

Figure 6. XRS7004F Device Pinout (Top View) .......................................................................................................................................... 19

Figure 7. Top Level Block Diagram ................................................................................................................................................................ 28

Figure 8. Read Access using MDIO ................................................................................................................................................................ 31

Figure 9. Write Access using MDIO ................................................................................................................................................................ 31

Figure 10. Write Access using I2C ................................................................................................................................................................. 32

Figure 11. Read Access using I2C ................................................................................................................................................................. 33

XRS7000 and XRS3000 User Manual, Version 1.3

Contents

Figure 12. I2C Write............................................................................................................................................................................................ 34

Figure 13. I2C ReadAddress ............................................................................................................................................................................ 35

Figure 14. I2C ReadData ................................................................................................................................................................................... 36

Figure 15. RS Block Diagram ........................................................................................................................................................................... 38

Figure 16. Forwarding Path ............................................................................................................................................................................. 39

Figure 17. RS Inbound and Outbound Processing Blocks ...................................................................................................................... 40

Figure 18. Ethernet Frame Timestamp Point .............................................................................................................................................. 41

Figure 19. Forwarding Decision ...................................................................................................................................................................... 43

Figure 20. Inbound Policy ................................................................................................................................................................................. 45

Figure 21. Ethernet Frame with Time Trailer............................................................................................................................................... 47

Figure 22. Ethernet Frame with Management Trailer .............................................................................................................................. 48

Figure 23. Management Trailer with 3-port RS and 8-bit offset ........................................................................................................... 49

Figure 24. MAC Address Entry ........................................................................................................................................................................ 49

Figure 25. Address Learning ............................................................................................................................................................................ 51

Figure 26. Address Aging.................................................................................................................................................................................. 52

Figure 27. MAC Address Search & Forwarding Decision ........................................................................................................................ 54

Figure 28. Priority Queues (three ports shown) ......................................................................................................................................... 57

Figure 29. Frame Early Drop Algorithm ........................................................................................................................................................ 58

Figure 30. Frame from normal port (or non-PRP frame from PRP port) ............................................................................................. 59

Figure 31. HSR Redundant Port Forwarding Logic .................................................................................................................................. 60

Figure 32. PRP Redundant Port Forwarding Logic ................................................................................................................................... 63

Figure 33. RTC Interfaces ...............................................................................................................................................................................107

Figure 34. TS Interfaces ..................................................................................................................................................................................112

Figure 35. Reset Timing ..................................................................................................................................................................................124

Figure 36. RGMII Timing ..................................................................................................................................................................................125

Figure 37. RMII Clocking Option 1 ...............................................................................................................................................................126

Figure 38. RMII Clocking Option 2 ...............................................................................................................................................................126

Figure 39. RMII Timing .....................................................................................................................................................................................127

Figure 40. I2C Timing .......................................................................................................................................................................................128

Figure 41. MDIO Timing ...................................................................................................................................................................................129

Figure 42. EQFP144 Package Dimensions ...............................................................................................................................................131

Figure 43. FBGA256 Package Dimensions...............................................................................................................................................133

Tables

Table 1. Device Features ...................................................................................................................................................................................... 2

Table 2. Pin Types ............................................................................................................................................................................................... 12

Table 3. EQFP144 Package RGMII Pin Definitions ................................................................................................................................... 12

Table 4. EQFP144 Package RMII Pin Definitions ...................................................................................................................................... 14

Table 5. EQFP144 Package Register Access and Interrupt Pin Definitions ..................................................................................... 14

Table 6. EQFP144 Package Time Synchronization Pin Definitions ..................................................................................................... 15

Table 7. EQFP144 Package Clock and Reset Pin Definitions ............................................................................................................... 15

Table 8. EQFP144 Package Power and Ground Pin Definitions........................................................................................................... 15

Table 9. EQFP144 Package Other Pin Definitions .................................................................................................................................... 17

Table 10. Pin Types ............................................................................................................................................................................................. 20

Table 11. FBGA256 Package RGMII Pin Definitions ................................................................................................................................ 20

Table 12. FBGA256 Package RMII Pin Definitions ................................................................................................................................... 21

Table 13. FBGA256 Package Register Access and Interrupt Pin Definitions................................................................................... 22

Table 14. FBGA256 Package Time Synchronization Pin Definitions................................................................................................... 22

Table 15. FBGA256 Package Clock and Reset Pin Definitions............................................................................................................. 22

XRS7000 and XRS3000 User Manual, Version 1.3

型号	ARWSC-XRS7004E.*13066556	ARWSC-XRS7004E
描述	Ethernet Switch 4-Port 1000Mbps 144-Pin EQFP EP	Single-chip gigabit Ethernet switch supporting HSR and PRP
ECCN (US)	5A991.c.10.b	5A991.c.10.b
Part Status	Active	Active
Number of Primary Switch Ports	4	4
PHY/Transceiver Interface	RMII	RMII
Minimum Operating Supply Voltage	3.135V	3.135V
Typical Operating Supply Voltage	3.3V	3.3V
Maximum Operating Supply Voltage	3.45V	3.45V
Power Supply Type	Single	Single
Fiber Support	No	No
Integrated LED Drivers	No	No
VLAN Support	Yes	Yes
JTAG Support	No	No
Minimum Operating Temperature (°C)	-40	-40
Maximum Operating Temperature (°C)	100	100
Supplier Package	EQFP EP	EQFP EP
Pin Count	144	144
Mounting	Surface Mount	Surface Mount
Package Height	1.45	1.45
Package Length	20	20
Package Width	20	20
PCB changed	144	144