2Gb DDR3L – AS4C128M16D3L
Revision History
AS4C128M16D3L - 96-ball FBGA PACKAGE
Revision
Rev 1.0
Rev 2.0
Details
Preliminary datasheet
Added "Backward compatible to VDD & VDDQ = 1.5V +/-
0.075V" - page 2
Updated Table 12. Recommended DC Operating
Conditions – page 21
Added CL=5 & CL=6 to Table 18 – page 26
Date
April 2014
August 2014
Confidential
1
Rev. 2.0
Aug. /2014
2Gb DDR3L – AS4C128M16D3L
128M x 16 bit DDR3L Synchronous DRAM (SDRAM)
Confidential
Features
JEDEC Standard Compliant
Power supplies: V
DD
& V
DDQ
= 1.35V
Backward compatible to V
DD
& V
DDQ
= 1.5V ±0.075V
Operating temperature:
- Commercial (0 ~ 95°C)
- Industrial (-40 ~ 95°C)
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
- DQS & DQS#
8 internal banks for concurrent operation
8n-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Additive Latency (AL): 0, CL-1, CL-2
Programmable Burst lengths: 4, 8
Burst type: Sequential / Interleave
Output Driver Impedance Control
8192 refresh cycles / 64ms
- Average refresh period
7.8μs @ -40
℃ ≦
TC
≦
+85
℃
3.9μs @ +85
℃ ＜
TC
≦
+95
℃
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
96-ball 9 x 13 x 1.2mm FBGA package
- Pb and Halogen Free
Advanced (Rev. 2.0, Aug. /2014)
Overview
The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8
bank devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to 1600
Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK#
falling). All I/Os are synchronized with differential DQS
pair in a source synchronous fashion.
These devices operate with a single 1.35V -0.067V
/+0.1V power supply and are available in BGA
packages.
Table 1. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
Table 2. Ordering Information
Product part No
AS4C128M16D3L-12BCN
AS4C128M16D3L-12BIN
Org
128M x 16
128M x 16
Temperature
Commercial (Extended)
0°C to 95°C
Industrial
-40°C to 95°C (Extended)
Package
96-ball FBGA
96-ball FBGA
Confidential
2
Rev. 2.0
Aug. /2014
2Gb DDR3L – AS4C128M16D3L
Figure 1. Ball Assignment (FBGA Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
2
DQ13
VDD
DQ11
VDDQ
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
CS#
BA0
A3
A5
A7
RESET#
3
DQ15
VSS
DQ9
UDM
DQ0
LDQS
LDQS#
DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
A13
…
7
DQ12
UDQS#
.
UDQS
DQ8
LDM
DQ1
VDD
DQ7
CK
CK#
A10/AP
NC
A12/BC #
8
VDDQ
DQ14
DQ10
VSSQ
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VREFCA
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
BA1
A4
A6
A8
A1
A11
NC
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3
Rev. 2.0
Aug. /2014
2Gb DDR3L – AS4C128M16D3L
Figure 2. Block Diagram
CK
CK#
CKE
RESET#
CS#
RAS#
CAS#
WE#
Row
Decoder
DLL
CLOCK
BUFFER
16M x 16
CELL ARRAY
(BANK #0)
Column Decoder
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
Row
Decoder
16M x 16
CELL ARRAY
(BANK #1)
Column Decoder
Row
Decoder
16M x 16
CELL ARRAY
(BANK #2)
Column Decoder
A10/AP
A12/BC#
Row
Decoder
COLUMN
COUNTER
MODE
REGISTER
16M x 16
CELL ARRAY
(BANK #3)
Column Decoder
A0~A9
A11
A13
BA0
BA1
BA2
Row
Decoder
ADDRESS
BUFFER
16M x 16
CELL ARRAY
(BANK #4)
Column Decoder
REFRESH
COUNTER
RZQ
Row
Decoder
ZQCL
ZQCS
ZQ
CAL
16M x 16
CELL ARRAY
(BANK #5)
Column Decoder
VSSQ
LDQS
LDQS#
UDQS
UDQS#
DATA
STROBE
BUFFER
DQ
Buffer
Row
Decoder
16M x 16
CELL ARRAY
(BANK #6)
Column Decoder
DQ0
DQ15
ODT LDM
UDM
Row
Decoder
~
16M x 16
CELL ARRAY
(BANK #7)
Column Decoder
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Rev. 2.0
Aug. /2014
2Gb DDR3L – AS4C128M16D3L
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling
of on-die termination, and some other events are not captured in full detail
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
E
Self
Refresh
from any
RESET
state
ZQ
Calibration
ZQCL,ZQCS
Idle
SR
ZQCL
MRS
SR
X
REF
Refreshing
PD
ACT
E
PD
X
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Active
Power
Down
PD
X
PD
E
Activating
Precharge
Power
Down
Bank
Activating
RE
AD
TE
RI
W
WR
ITE
A
WRITE
READ
Writing
READ
WRITE
DA
EA
R
Reading
WRITE A
READ A
EA
RIT
W
PRE, PREA
RE
AD
A
PR
Writing
EA
PR
E,
PR
Reading
E
,P
RE
A
Automatic Sequence
Command Sequence
Precharging
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Rev. 2.0
Aug. /2014
