AS4C256M16D3LA-12BIN
Revision History
4Gb
AS4C256M16D3LA-12BIN
-
96
ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
May.
2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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Rev. 1.0 May 2016
AS4C256M16D3LA-12BIN
256M x 16 bit DDR3L Synchronous DRAM (SDRAM)
Features
•
JEDEC Standard Compliant
•
Power supplies: V
DD
& V
DDQ
= +1.35V
•
Backward compatible to V
DD
& V
DDQ
= 1.5V ±0.075V
•
Operating temperature: -40~95°C (TC)
•
Supports JEDEC clock jitter specification
•
Fully synchronous operation
•
Fast clock rate: 800 MHz
•
Differential Clock, CK & CK#
•
Bidirectional differential data strobe
- DQS & DQS#
•
8 internal banks for concurrent operation
•
8n-bit prefetch architecture
•
Pipelined internal architecture
•
Precharge & active power down
•
Programmable Mode & Extended Mode registers
•
Additive Latency (AL): 0, CL-1, CL-2
•
Programmable Burst lengths: 4, 8
•
Burst type: Sequential / Interleave
•
Output Driver Impedance Control
•
8192 refresh cycles / 64ms
- Average refresh period
7.8μs @ -40°C
≦TC≦
+85°C
3.9μs @ +85°C
＜TC≦
+95°C
•
Write Leveling
•
ZQ Calibration
•
Dynamic ODT (Rtt_Nom & Rtt_WR)
•
RoHS compliant
•
Auto Refresh and Self Refresh
•
96-ball 9 x 13 x 1.0mm FBGA package
- Pb and Halogen Free
Overview
The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 4Gb chip is organized as 32Mbit x 16 I/Os x 8
bank devices. These synchronous devices achieve
high speed double-data-rate transfer rates of up to
1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK#
falling). All I/Os are synchronized with differential DQS
pair in a source synchronous fashion.
These devices operate with a single 1.35V -0.067V
/+0.1V power supply and are available in BGA packages.
Table 1. Ordering Information
Product part No
AS4C256M16D3LA-12BIN
Org
256M
x
16
Temperature
Industrial
-40°C
to
95°C
Max Clock (MHz)
800
Package
96-ball
FBGA
Table 2. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
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AS4C256M16D3LA-12BIN
Figure 1. Ball Assignment (FBGA Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
2
DQ13
VDD
DQ11
VDDQ
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
CS#
BA0
A3
A5
A7
RESET#
3
DQ15
VSS
DQ9
UDM
DQ0
LDQS
LDQS#
DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
A13
…
7
DQ12
UDQS#
.
UDQS
DQ8
LDM
DQ1
VDD
DQ7
CK
CK#
A10/AP
NC
A12/BC #
8
VDDQ
DQ14
DQ10
VSSQ
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VREFCA
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
BA1
A4
A6
A8
A1
A11
A14
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Rev. 1.0 May 2016
AS4C256M16D3LA-12BIN
Figure 2. Block Diagram
Row
Decoder
CK
CK#
CKE
DLL
CLOCK
BUFFER
32M x 16
CELL ARRAY
(BANK #0)
Column Decoder
RESET#
Row
Decoder
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
32M x 16
CELL ARRAY
(BANK #1)
Column Decoder
Row
Decoder
32M x 16
CELL ARRAY
(BANK #2)
Column Decoder
A10/AP
A12/BC#
Row
Decoder
COLUMN
COUNTER
MODE
REGISTER
32M x 16
CELL ARRAY
(BANK #3)
Column Decoder
A0~A9
A11
A13
A14
BA0
BA1
BA2
Row
Decoder
ADDRESS
BUFFER
32M x 16
CELL ARRAY
(BANK #4)
Column Decoder
Row
Decoder
REFRESH
COUNTER
RZQ
ZQCL
ZQCS
ZQ
CAL
32M x 16
CELL ARRAY
(BANK #5)
Column Decoder
VSSQ
Row
Decoder
LDQS
LDQS#
UDQS
UDQS#
DATA
STROBE
BUFFER
32M x 16
CELL ARRAY
(BANK #6)
Column Decoder
DQ
Buffer
DQ0
Row
Decoder
DQ15
ODT LDM
UDM
~
32M x 16
CELL ARRAY
(BANK #7)
Column Decoder
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Rev. 1.0 May 2016
AS4C256M16D3LA-12BIN
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands
to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
SR
SR E
X
Self
Refresh
from any
RESET
state
ZQCL
MRS
ZQ
Calibration
ZQCL,ZQCS
Idle
REF
Refreshing
E
PD X
PD
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Active
Power
Down
PD
X
PD
E
Activating
Precharge
Power
Down
Bank
Activating
RE
AD
ITE
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
A
W
TE
RI
WR
WRITE
READ
Writing
WRITE
READ
AD
RE
A
Reading
WRITE A
READ A
EA
RIT
W
RE
AD
A
PRE, PREA
Writing
PR
E
,P
RE
A
P
E,
PR
A
RE
Reading
Automatic Sequence
Command Sequence
Precharging
Confidential
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Rev. 1.0 May 2016
