AS4C8M32S-6TIN
AS4C8M32S-7TCN
Revision History
AS4C8M32S -
86-pin TSOPII
PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
Mar.
2016
AS4C8M32S-6TIN
AS4C8M32S-7TCN
Features
•
Fast access time from clock: 5/5.4 ns
Overview
The 256Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 256 Mbits. It is
internally configured as 4 Banks of 2M word x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
•
Fast clock rate: 166/143MHz
•
Fully synchronous operation
•
Internal pipelined architecture
•
2M word x 32-bit x 4-bank
•
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
•
Auto Refresh and Self Refresh
•
4096 refresh cycles/64ms
•
CKE power down mode
•
Single +3.3V
±
0.3V power supply
•
Operating Temperature:
- Commercial (0~70°C)
- Industrial (-40~85°C)
•
Interface: LVTTL
•
86-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
Table 1.
Key Specifications
AS4C8M32S
tCK3
tAC3
tRAS
tRC
Clock Cycle time (min.)
Access time from CLK (max.)
Row Active time (min.)
Row Cycle time (min.)
-6/7
6/7
5/5.4
42/42
60/63
Table 2. Ordering Information
Part Number
AS4C8M32S-6TIN
AS4C8M32S-7TCN
Frequency
166MHz
143MHz
Package
86 Pin TSOP II
86 Pin TSOP II
C:Commercial
I:Industrial
Temperature
Industrial
Commercial
Temp Range
-40~85°C
0~70°C
T:indicates TSOP II package
N:indicates Pb free and Halogen free
AS4C8M32S-6TIN
AS4C8M32S-7TCN
Figure 1. Pin Assignment
(Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
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AS4C8M32S-6TIN
AS4C8M32S-7TCN
Figure 2. Block Diagram
CKE
Row
Decoder
CLK
CLOCK
BUFFER
2M x 32
CELL ARRAY
(BANK #A)
Column Decoder
CS#
RAS#
CAS#
WE#
DQ31
DQM0 ~ DQM3
Row
Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
2M x 32
CELL ARRAY
(BANK #B)
Column Decoder
A0
A9
A11
BA0
BA1
Row
Decoder
ADDRESS
BUFFER
~
2M x 32
CELL ARRAY
(BANK #C)
Column Decoder
REFRESH
COUNTER
Row
Decoder
2M x 32
CELL ARRAY
(BANK #D)
Column Decoder
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~
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
DQ
Buffer
DQ0
AS4C8M32S-6TIN
AS4C8M32S-7TCN
Pin Descriptions
Table 3. Pin Details
Symbol
CLK
Type
Input
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. When all banks are in the idle state,
deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes,
where CKE becomes asynchronous until exiting the same mode. The input buffers,
including CLK, are disabled during Power Down and Self Refresh modes, providing low
standby power.
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used
latched in mode register set.
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address
A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto
Precharge) to select one location out of the 2M available in the respective bank. During a
Precharge command, A10 is sampled to determine if all banks are to be precharged (A10
= HIGH). The address inputs also provide the op-code during a Mode Register Set or
Special Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH" either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH" the BankActivate command is selected and the bank designated by BA
is turned on to the active state. When the WE# is asserted "LOW" the Precharge
command is selected and the bank designated by BA is switched to the idle state after
the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
is held "HIGH" and CS# is asserted "LOW" the column access is started by asserting CAS#
"LOW". Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH".
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask: Data Input Mask:
DQM0-DQM3 are byte specific. Input data
is masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24,
DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
CKE
Input
BA0,
BA1
A0-A11
Input
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
DQM0 -
DQM3
Input
DQ0- Input/Ou
Data I/O:
The DQ0-31 input and output data are synchronized with the positive edges of
DQ31
tput CLK. The I/Os are byte-maskable during Reads and Writes.
NC
V
DDQ
V
SSQ
V
DD
V
SS
Confidential
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Supply
Power Supply:
+3.3V±0.3V
Supply
Ground
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