iPEM
4.8 Gb SDRAM-DDR2
AS4DDR264M72PBG1
64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Package:
•
Proprietary Enchanced Die Stacked iPEM
•
208 Plastic Ball Grid Array (PBGA), 16 x 23mm
•
1.00mm ball pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4n-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes (I/T Version)
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V
±0.1V
common core power and I/O supply
Programmable CAS latency: 3, 4, 5, 6 or 7
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5
Write latency = Read latency - 1* tCK
Organized as 64M x 72
Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical
BENEFITS
61% Space Savings
55% I/O reduction vs Individual package
approach
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density in future
Pin/Function equivalent to White
W3H64M72E-xBSx
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
64 Meg x 72
8 Meg x 16 x 8 Banks
8K
A0 A12 (8k)
BA0 BA2 (8)
A0 A9 (1K)
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-2
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VSSQ
VCCL
VSSDL
CS\
WE\
RAS\
CAS\
CKE\
ODT
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
CKx,CKx\
A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCCQ
VSSQ
VCCL
A
VSSDL
B
VCCQ
VSSQ
VCCL
VSSDL
C
VCCQ
VSSQ
VCCL
VSSDL
D
VCCQ
VSSQ
VCCL
VSSDL
DQ64-71
ODT
LDM4
DQ0-15 B
DQ16-31 C
UDM4
DQ32-47 D
DQ48-63
AS4DDR264M72PBG1
Rev. 3.1 01/10
Micross Components reserves the right to change products or specifications without notice.
1
iPEM
4.8 Gb SDRAM-DDR2
AS4DDR264M72PBG1
SDRAM-DDRII PINOUT TOP VIEW
1
A
B
C
D
E
F
G
H
J
K
L
Vcc
Vss
DQ35
DQ52
LDM3
DQ38
UDM3
Vcc
Vss
Vcc
2
Vcc
Vss
NC
DQ51
DQ36
LDM2
DQ54
DQ44
A6
A0
A2
3
Vss
NC
NC
NC
DQ33
DQ49
DQ60
DQ41
A10
A11
A4
4
Vcc
NC
NC
NC
NC
DQ43
DQ57
DQ46
A9
Vcc
A8
DQ15
DQ24
DQ26
LDQS0
DQ21
DQ2
CK4
Vcc
4
5
Vcc
NC
NC
NC
BA2
DQ59
UDM2
DQ62
Vcc
Vss
Vcc
UDQS0\
DQ31
DQ23
DQ7
DQ18
RAS\
CS\
Vcc
5
6
Vss
NC
NC
NC
NC
NC
Vss
Vcc
Vss
Vref
Vss
Vcc
Vss
ODT
7
Vcc
NC
NC
DQ50
DQ39
DQ55
DQ63
UDQS2\
Vcc
Vss
Vcc
DQ30
UDM0
DQ27
8
Vcc
NC
DQ34
DQ53
LDQS2
DQ58
DQ56
DQ47
A3
Vcc
BA0
DQ14
DQ25
DQ11
9
Vss
NC
CK3
DQ37
LDQS3
DQ42
DQ40
10
Vcc
Vss
CK3\
CK2\
DQ48
11
Vss
Vcc
Vss
CK2
DQ32
A
B
C
D
E
LDQS2\ LDQS3\
F
DQ61
DQ45
G
UDQS2 UDQS3 UDQS3\
H
A12
A1
A5
DQ9
DQ28
DQ17
DQ1
WE\
DQ65
DQ67
Vss
9
RFU
BA1
A7
DQ12
DQ22
LDM0
DQ4
DQ19
DQ68
Vss
Vcc
10
Vcc
Vss
Vcc
J
K
L
M
UDQS1\ UDQS1 UDQS0
N
P
R
T
U
V
W
DQ13
DQ29
DQ8
DQ10
LDQS1
DQ5
CK1
CK4\
Vss
3
UDM1
M
DQ6
LDM1
DQ20
DQ3
Vss
Vcc
Vss
11
N
p
R
T
U
V
W
LDQS1\ LDQS0\
DQ0
CK0
Vss
Vcc
Vss
1
DQ16
CK0\
CK1\
Vss
Vcc
2
LDQS4\ UDQS4 UDQS4\
LDQS4
CAS\
DQ66
Vss
6
DQ71
DQ64
DQ69
Vcc
7
CKE
DQ70
LDM4
Vcc
8
Ground
CNTRL
Data I/O
Array Power
Level REF.
UNPOPULATED
NC
Address
RFU
AS4DDR264M72PBG1
Rev. 3.1 01/10
Micross Components reserves the right to change products or specifications without notice.
2
iPEM
4.8 Gb SDRAM-DDR2
AS4DDR264M72PBG1
BGA Locations
P6
C9,C10,D10,D11,T1,T2,
U2,U3,V3,V4
T8
V5
U5
U6
T9
G5,H1,M11,N7,
F1,F2,P10,P11,V8
H9,H10,M2,M3,R7
H7,H11,M1,M5,R8
E8,E9,R3,R4,T6
F10,F11,P1,P2,R6
J2,J3,J4,J8,J9,K2,
K3,K9,L2,L3,L4,L9,L10
Symbol
ODT
CKx, CKx\
CKE
CS\
RAS\
CAS\
WE\
UDMx
LDMx
UDQSx
UDQSx\
LDQSx
LDQSx\
Ax
Type
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
Input
Description
On-Die-Termination: Registered High enables on data bus termination
Differential input clocks, one set for each x16bits
Clock enable which activates all on silicon clocking circuitry
Chip Selects, one for each 16 bits of the data bus width
Command input which along with CAS\, WE\ and CS\ define operations
Command input which along with RAS\, WE\ and CS\ define operations
Command input which along with RAS\, CAS\ and CS\ define operations
One Data Mask cntl. for each upper 8 bits of a x16 word
One Data Mask cntl. For each lower 8 bits of a x16 word
Data Strobe input for upper byte of each x16 word
Differential input of UDQSx, only used when Differential DQS mode is enabled
Data Strobe input for lower byte of each x16 word
Differential input of LDQSx, only used when Differential DQS mode is enabled
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
J10
RFU
L8,K10,E5
BA0,BA1,BA2
C8,D1,D2,D7,D8,D9,E1,
DQx
E2,E3,E7,E10,E11,F3,
F4,F5,F7,F8,F9,G1,G2,
G3,G4,G7,G8,G9,G10,
G11,H2,H3,H4,H5,H8,
M4,M7,M8,M9,M10,N1,
N2,N3,N4,N5,N8,N9,
N10,N11,P3,P4,P5,P7,
P8,P9,R1,R2,R5,R9,
R10,R11,T3,T4,T5,T7,
T10,T11,U4,U7,U8,U9,
U10,V6,V7,V9
k6
Vref
A2,A4,A5,A7,A8,A10,
VCC
B1,B11,H6,J1,J5,J7,J11,
K4,K8,L1,L5,L7,L11,M6,
V1,V11,W2,W4,W5,
W7,W8,W10
A3,A6,A9,A11,B2,B10,
VSS
C1,C11,G6,J6,K1,K5,
K7,K11,L6,N6,U1,U11,
V2,V10,W1,W3,W6,
W9,W11
B3,B4,B5,B6,B7,B8,B9,
NC
C2,C3,C4,C5,C6,C7,D3,
D4,D5,D6,E4, E6, F6
A1
UNPOPULATED
Future Input
Input
Bank Address inputs
Input/Output Data bidirectional input/Output pins
Supply
Supply
SSTL_18 Voltage Reference
Core Power Supply
Supply
Core Ground return
No connection
Unpopulated ball matrix location (location registration aid)
AS4DDR264M72PBG1
Rev. 3.1 01/10
Micross Components reserves the right to change products or specifications without notice.
3
iPEM
4.8 Gb SDRAM-DDR2
AS4DDR264M72PBG1
DESCRIPTION
The 4.8Gb DDR2 SDRAM, a high-speed CMOS, dynamic
random-access memory containing 4,831,838,208 bits.
Each of the
fi
ve chips in the MCP are internally configured
as 8-bank DRAM. The block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
The 4.8Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer
two data words per clock cycle at the I/O balls. A
single read or write access for the x72 DDR2 SDRAM
effectively consists of a single 4n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and four
corresponding
n-bit-wide,
one-half-clock-cycle data
transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and
one for the upper byte (UDQS, UDQS#).
The MCP DDR2 SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data
is referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another
write.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
A self refresh mode is provided, along with a power-
saving power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_18. All full drive-strength outputs are SSTL_18-
compatible.
•
The functionality and the timing specifications
discussed in this data sheet are for the DLLenabled
mode of operation.
•
Throughout the data sheet, the various
fi
gures and
text refer to DQs as ¡°DQ.¡± The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0¨CDQ7), DM refers to
LDM and DQS refers to LDQS. For the upper byte
(DQ8¨CDQ15), DM refers to UDM and DQS refers to
UDQS.
•
Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
•
Any specific requirement takes precedence over a
general statement.
GENERAL NOTES
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
The following sequence is required for power up and
initialization and is shown in Figure 4 on page 5.
AS4DDR264M72PBG1
Rev. 3.1 01/10
Micross Components reserves the right to change products or specifications without notice.
4
iPEM
4.8 Gb SDRAM-DDR2
AS4DDR264M72PBG1
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
V
DD
V
DD
L
V
DD
Q
V
TT
1
V
REF
T0
t
CK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
Tm0
t
VTD1
CK#
CK
t
CL
t
CL
LVCMOS 2
SSTL_18
2
CKE
LOW LEVEL LOW LEVEL
ODT
3
Command
15
DM
NOP4
PRE
LM5
LM
6
LM7
LM8
PRE9
REF10
REF
LM11
LM12
LM13
Valid
16
Address
3
A10 = 1
Code
Code
Code
Code
A10 = 1
Code
Code
Code
Valid
15
DQS
DQ
15
High-Z
High-Z
High-Z
R
TT
T = 200µs (MIN)
Power-up:
V
DD
and stable
clock
(CK,
CK#)
T = 400ns
(MIN)16
tRPA
EMR(2)
tMRD
tMRD
EMR(3)
EMR
tMRD
tMRD
tRPA
tRFC
tRFC
See note 17
tMRD
tMRD
EMR with
OCD exit
tMRD
MR without
DLL RESET
MR with
DLL RESET
EMR with
OCD
default
200
cycles
of
CK
are required
before
a READ
command can be
issued.
Normal
operation
Indicates a
break
in
time scale
Don’t
care
AS4DDR264M72PBG1
Rev. 3.1 01/10
Micross Components reserves the right to change products or specifications without notice.
5
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