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AS5C512K8ECJ-35/IT

Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36

器件类别:存储   

厂商名称:Micross

厂商官网:https://www.micross.com

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Micross
零件包装代码
SOJ
包装说明
SOJ,
针数
36
Reach Compliance Code
compliant
ECCN代码
3A991.B.2.A
Is Samacsys
N
最长访问时间
35 ns
JESD-30 代码
R-CDSO-J36
JESD-609代码
e0
长度
23.4823 mm
内存密度
4194304 bit
内存集成电路类型
STANDARD SRAM
内存宽度
8
功能数量
1
端子数量
36
字数
524288 words
字数代码
512000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
512KX8
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
SOJ
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
4.064 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN LEAD
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
11.3538 mm
Base Number Matches
1
文档预览
SRAM
Austin Semiconductor, Inc.
512K x 8 SRAM
HIGH SPEED SRAM with
REVOLUTIONARY PINOUT
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-95600
•SMD 5962-95613
•MIL-STD-883
AS5C512K8
PIN ASSIGNMENT
(Top View)
36-Pin SOJ (DJ & ECJ)
36-Pin CLCC (EC)
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +5V Power Supply +/- 10%
• Data Retention Functionality Testing (Contact Factory)
• Cost Efficient Plastic Packaging
• Extended Testing Over -55ºC to +125ºC for plastics
• Plastic 36 pin PSOJ is fully compatible with the
Ceramic 36 pin SOJ
• 3.3V Future Offering
36-Pin Flat Pack (F)
OPTIONS
• Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
• Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
Industrial (-40
o
C to +85
o
C)
• Package(s)
Ceramic LCC
Ceramic Flatpack
Plastic SOJ
Ceramic SOJ
• 2V data retention/low power
• Radiation Tolerant (EPI)
MARKING
-12
-15
-17
-20
-25
-35
-45
XT
IT
GENERAL DESCRIPTION
The AS5C512K8 is a high speed SRAM. It offers flexibility in
high-speed memory applications, with chip enable (CE\) and output
enable (OE\) capabilities. These features can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +5V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5C512K8DJ offers the convenience and reliability of the
AS5C512K8 SRAM and has the cost advantage of a durable plastic.
The AS5C512K8DJ is footprint compatible with 36 pin CSOJ
package of the SMD 5692-95600.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
EC
F
DJ
ECJ
No. 210
No. 307
No. 903
No.503
L (Consult Factory)
E
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5C512K8
Rev. 6.2 06/05
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
AS5C512K8
DQ8
INPUT BUFFER
ROW DECODER
I/O
CONTROLS
4,194,304-BIT
MEMORY ARRAY
1024 ROWS X
4096 COLUMNS
A0-A18
DQ1
CE\
COLUMN DECODER
OE\
WE\
*POWER
DOWN
*On the low voltage Data Retention option.
PIN FUNCTIONS
A0 - A18
Address Inputs
Write Enable
Chip Enable
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
TRUTH TABLE
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
X = Don’t Care
WE\
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CE\
OE\
I/O
0
- I/O
7
V
CC
V
SS
NC
AS5C512K8
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
AS5C512K8
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
Voltage on Vcc Supply Relative to Vss
Vcc ..............................................................................-.5V to +7.0V a stress rating only and functional operation of the device at
Storage Temperature (Plastic)......................-65°C to +150°C these or any other conditions above those indicated in the
Storage Temperature (Ceramic)...................-55°C to +125°C operation section of this specification is not implied. Exposure
Short Circuit Output Current (per I/O)…........................20mA to absolute maximum rating conditions for extended periods
Voltage on any Pin Relative to Vss.................-.5V to Vcc+1V may affect reliability.
Maximum Junction Temperature**..............................+150°C ** Junction temperature depends upon package type, cycle
Power Dissipation ................................................................1W time, loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C & -40
o
C < T
A
< +85
o
C ; Vcc = 5V +10%)
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CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
CONDITIONS
T
A
= 25 C, f = 1MHz
V
IN
= 0
o
SYMBOL
C
I
Co
MAX
12
14
UNITS
pF
pF
NOTES
4
4
AS5C512K8
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS5C512K8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C or -40
o
C to +85
o
C; Vcc = 5V +10%)
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AS5C512K8
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
AS5C512K8
Q
167 ohms
1.73V
C=30pF
Q
167 ohms
1.73V
C=5pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
4.
5.
6.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
7.
8.
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L Version Only)
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Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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