AUGUST 2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 55 ns
Low power consumption:
Operating current : 30 mA (TYP.)
Standby current : 4 µA (TYP.)
Single 2.7V ~ 5.5V power supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage :1.5V (MIN.)
All products ROHS Compliant
Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
32-pin 400 mil TSOP-II
GENERAL DESCRIPTION
The AS6C4008 is a 4,194,304-bit low power
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C4008 is well designed for very low power
system applications, and particularly well suited for
battery back-up non-volatile memory application.
The AS6C4008 op erates from a sing le p owe r
sup p ly of 2.7V~ 5.5Vand all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
AS6C4008
Operating
Temperature
-40 ~ +85
℃
Vcc Range
2.7 ~ 5.5V
Speed
55ns
Power Dissipation
Standby(I
SB1
TYP.) Operating(Icc,TYP.)
4µA(LL)
30mA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION**
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Vcc
Vss
512Kx8
MEMORY ARRAY
A0 - A18
DQ0 – DQ7
DECODER
A0-A18
CE#
WE#
OE#
V
CC
V
SS
NC
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
WE#
OE#
CONTROL
CIRCUIT
AUG/09, v 1.4
Alliance Memory Inc
Page 1 of 14
AUGUST 2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
32
31
30
29
28
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE#
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
AS6C4008
SOP/ P-DIP
6
7
8
9
10
11
12
13
14
15
16
27
26
25
24
23
22
21
20
19
18
17
AS6C4008
TSOP-I/STSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP-II
32
31
30
29
28
27
26
VCC
A15
A17
W E#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
G
DQ4
H
DQ3
A
9
A10
A11
A12
A13
A14
DQ7 OE# CE#
A16
A15
DQ3
AS6C4008
25
24
23
22
21
20
19
18
17
A
B
C
D
E
F
A0
DQ4
DQ5
Vss
Vcc
DQ6
A1
A2
NC
WE#
NC
A3
A4
A5
A6
A7
A8
DQ0
DQ1
Vcc
Vss
A18
A17
DQ2
1
2
3
4
TFBGA
5
6
AUG/09, v 1.4
Alliance Memory Inc
Page 2 of 14
AUGUST
2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
-40 to 85(I grade)
T
STG
P
D
I
OUT
T
SOLDER
-65 to 150
1
50
260
RATING
-0.5 to 6.5
0 to 70(C grade)
UNIT
V
C
o
C
o
W
mA
C
o
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
Note: H = V
IH
, L = V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
SYMBOL
V
CC
TEST CONDITION
MIN.
2.7
2.4
2.2
- 0.2
- 0.2
-1
-1
2.4
-
-
TYP.
3.0
-
-
-
-
-
-
-
-
30
*3
V
IH
*1
V
IL
*1
I
LI
I
LO
V
OH
V
OL
I
CC
V
cc
: 4.5 ~ 5.5V
V
cc
: 2.7 ~ 4.5V
V
cc
: 4.5 ~ 5.5V
V
cc
: 2.7 ~ 4.5V
V
CC
≧
V
IN
≧
V
SS
V
CC
≧
V
OUT
≧
V
SS
,
Output Disabled
I
OH
= -1mA
I
OL
= 2mA
Cycle time = Min.
- 55
CE# = 0.2V, I
I/O
= 0mA
other pins at 0.2V or V
CC
- 0.2V
Cycle time = 1µs
CE# = 0.2V, I
I/O
= 0mA
other pins at 0.2V or V
CC
- 0.2V
-LL
CE#
≧V
CC
- 0.2V
-LLE/-LLI
MAX.
UNIT
5.5
V
V
CC
+0.3
V
V
CC
+0.3
0.8
0.6
1
1
-
0.4
60
V
V
V
µA
µA
V
V
mA
Average Operating
Power supply Current
I
CC1
Standby Power
Supply Current
I
SB1
-
-
-
4
4
4
10
50
*4
50
*4
mA
µA
µA
Notes: 1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
2. Over/Undershoot specifications are characterized, not 100% tested.
3. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25
?
4. 25µA for special request
AUG/09, v 1.4
Alliance Memory Inc
Page 3 of 14
AUGUST
2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
= 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
AS6C4008-55
MIN.
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
5
-
-
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM.
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
AS6C4008-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
AUG09 v1.4
Alliance Memory Inc
Page 4 of 14
AUGUST
2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled) (1,2)
t
RC
Address
t
AA
Dout
Previous Data Valid
t
OH
Data Valid
READ CYCLE 2
(CE# and OE# Controlled) (1,3,4,5)
t
RC
Address
t
AA
CE#
t
ACE
OE#
t
OLZ
t
OE
t
OH
t
OHZ
t
CHZ
Data Valid
High-Z
t
CLZ
Dout
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low
.
3.Address must be valid prior to or coincident with CE# = low
,
; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
AUG09 v1.4
Alliance Memory Inc
Page 5 of 14
