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AS7C1025-20JIN

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, SOJ-32

器件类别:存储    存储   

厂商名称:Alliance Memory

器件标准:

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
SOJ
包装说明
0.400 INCH, ROHS COMPLIANT, SOJ-32
针数
32
Reach Compliance Code
compli
ECCN代码
3A991.B.2.B
最长访问时间
20 ns
JESD-30 代码
R-PDSO-J32
JESD-609代码
e3/e6
长度
20.955 mm
内存密度
1048576 bi
内存集成电路类型
STANDARD SRAM
内存宽度
8
功能数量
1
端子数量
32
字数
131072 words
字数代码
128000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
128KX8
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
245
认证状态
Not Qualified
座面最大高度
3.683 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
PURE MATTE TIN/TIN BISMUTH
端子形式
J BEND
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
10.16 mm
Base Number Matches
1
文档预览
March 2001
®
AS7C1025
AS7C31025
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Features
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: STANDBY
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
• Low power consumption: ACTIVE
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
• ESD protection
2000 volts
• Latch-up current
200 mA
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
Pin arrangement
32-pin TSOP II
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
Row decoder
512×256×8
Array
(1,048,576)
Sense amp
I/O0
WE
OE
CE
Column decoder
A9
A10
A11
A12
A13
A14
A15
A16
Control
circuit
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
Selection guide
AS7C1025-12
AS7C31025-12
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
AS7C1025-15
AS7C31025-15
15
4
85
85
5
5
AS7C1025
AS7C31025
AS7C1025
AS7C31025
AS7C1025-20
AS7C31025-20
20
5
80
80
5
5
Unit
ns
ns
mA
mA
mA
mA
12
3
AS7C1025
AS7C31025
AS7C1025
AS7C31025
130
100
5
5
3/23/01; v.1.0
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C1025
AS7C31025
®
Functional description
The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20 ns with output enable access times (t
OE
) of 6,7,8 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank
memory systems.
When
CE
is high the devices enter standby mode. The standard AS7C1025 is guaranteed not to exceed 27.5 mW power
consumption in standby mode, and typically requires only 5 mW Both devices also offer 2.0V data retention.
.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0-I/O7 is
written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with
output enable (
OE
) or write enable
(
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025) or 3.3V supply
(AS7C31025). The AS7C1025 and AS7C31025 are packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Device
AS7C1025
AS7C31025
Symbol
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–0.50
–65
–55
Max
+7.0
+5.0
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
V
W
o
C
o
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
Key: X = Don’t Care, L = Low, H = High
3/23/01; v.1.0
Alliance Semiconductor
P. 2 of 9
®
AS7C1025
AS7C31025
Recommended operating conditions
Parameter
Supply voltage
Device
AS7C1025
AS7C31025
AS7C1025
Input voltage
AS7C31025
commercial
industrial
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL†
Ambient operating temperature
V
IL
min = –3.0V for pulse width less than t
RC
/2.
Min
4.5
3.0
2.2
2.0
–0.5
0
–40
Nominal
5.0
3.3
Max
5.5
3.6
V
CC
+ 0.5
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
V
V
o
C
o
T
A
T
A
C
DC operating characteristics (over the operating range)
1
-12
Parameter
Sym
Test conditions
Device
Min
Max
1
Min
Input leakage
|
I
LI
|
V
CC
= Max, V
IN
= GND to V
CC
current
Output
leakage
current
Operating
power supply
current
|
I
LO
|
V
CC
= Max, CE = V
IH
, V
out
=
GND to V
CC
AS7C1025
I
CC
CE = V
IL
,
f
=
f
Max,
I
OUT
= 0 mA
AS7C31025
AS7C1025
AS7C31025
-15
Max
1
Min
-20
Max
1
Unit
µA
µA
2.4
1
130
100
50
50
5
5
0.4
2.4
1
120
85
40
40
5
5
0.4
2.4
1
110
80
40
40
5
5
0.4
mA
Standby
power supply
current
1
I
SB1
Output
voltage
V
OL
V
OH
I
SB
CE = V
IH
, f = f
Max
, f
OUT
= 0
mA
mA
V
V
AS7C1025
CE
V
CC
–0.2V, V
IN
0.2V or
V
IN
V
CC
–0.2V, f = 0, f
OUT
= 0 AS7C31025
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Shaded areas contain advance information.
Capacitance (
f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL
)
2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
3/23/01; v.1.0
Alliance Semiconductor
P. 3 of 9
AS7C1025
AS7C31025
®
Read cycle (over the operating range)
3,9
-12
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE
Low t
o output in low Z
CE Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
Min
12
3
0
0
0
Max
12
12
6
3
3
12
Min
15
3
0
0
0
-15
Max
15
15
7
4
4
15
Min
20
3
0
0
0
-20
Max
20
20
8
5
5
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
3
Notes
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
3,6,7,9
t
RC
Address
t
AA
D
OUT
Data valid
t
OH
Read waveform 2 (CE and OE controlled)
3,6,8,9
CE
t
OE
OE
D
OUT
Supply
current
t
PU
t
ACE
t
CLZ
50%
Data valid
t
PD
50%
I
CC
I
SB
t
OLZ
t
OHZ
t
CHZ
t
RC1
3/23/01; v.1.0
Alliance Semiconductor
P. 4 of 9
®
AS7C1025
AS7C31025
Write cycle (over the operating range)
11
-12
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
-15
Max
5
Min
15
12
12
0
9
0
8
0
3
Max
5
Min
20
12
12
0
12
0
12
0
3
-20
Max
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
Notes
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Min
12
8
8
0
8
0
6
0
3
Write waveform 1 ( WE controlled)
10,11
t
WC
t
AW
Address
t
WP
WE
t
AS
D
IN
t
WZ
D
OUT
t
DW
Data valid
t
OW
t
DH
t
AH
Write waveform 2 (CE controlled)
10,11
t
AW
Address
t
AS
CE
t
WP
WE
t
WZ
D
IN
D
OUT
t
DW
Data valid
t
DH
t
CW
t
WC
t
AH
3/23/01; v.1.0
Alliance Semiconductor
P. 5 of 9
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