AS7C181026LL-55BC,AS7C181026LL-55BC pdf中文资料,AS7C181026LL-55BC引脚图,AS7C181026LL-55BC电路-Datasheet-电子工程世界

文档预览

3UHOLPLQDU\LQIRUPDWLRQ

$6&//

9.ð,QWHOOLZDWWORZSRZHU&02665$0

)HDWXUHV

• Optimized design for battery operated portable systems

• Intelliwatt™ active power reduction circuitry

• Organization: 65,536 words × 16 bits

• 1.65V to 1.95V operating range

• High speed

- 55*/70/100 ns address access time

• Low power consumption

- Active: 19.5 mW max (100 ns cycle)

- Standby: 2 µW max

- Very low DC component in active power, 20 µA

• 1.20V data retention

• Easy memory expansion with CE, OE inputs

• LVTTL/LVCMOS-compatible, three-state I/O

• JEDEC registered packaging

- 44-pin TSOP II package

- 48-ball csp 8mm × 6mm BGA

• Center power and ground pins for low noise

• ESD protection

≥

2000 volts

• Latch-up current

≥

200 mA

• Industrial temperature range available (-40 to +85 °C)

• Other voltage versions available

- 2.3V to 3.0V (AS7C251026LL)

- 2.7V to 3.6V (AS7C31026LL)

65$0

/RJLFEORFNGLDJUDP

Power

reduction

I/O0–I/O7

I/O8–I/O15

I/O

buffer

3LQDUUDQJHPHQW

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

A12

Row decoder

64K × 16

Array

TSOP II

Control circuit

Column decoder

A10

A11

A12

A13

A14

A15

48-CSP Ball-Grid-Array package

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

A10

A11

I/O

6HOHFWLRQJXLGH

7C181026LL-55*

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum standby current

*For availability of 55 ns device, contact Alliance.

7C181026LL-70

7C181026LL-100

100

Unit

µA

',' %

$//,$1&(6(0,&21'8&725

$6&//

3UHOLPLQDU\LQIRUPDWLRQ

)XQFWLRQDOGHVFULSWLRQ

The AS7C181026LL is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 65,536 words × 16

bits. It is designed for portable applications where fast data access, long battery life, low heat dissipation, and simple interfacing are desired.

65$0

Equal address access and cycle times (t

, t

) of 55*/70/100 ns are ideal for high performance applications. The chip enable input CE

permits easy memory expansion with multiple-bank memory systems.

When CE is High, or when UB and LB are simultaneously pulled Low, the device enters standby mode. The AS7C181026LL is guaranteed not

to exceed 2.0 µW power consumption in CMOS standby mode. This device also offers data retention down to 1.5V.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the

rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs

have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins

with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output

drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and

read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.

The device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the

smallest possible footprint. This 48-ball JEDEC registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.

/RZSRZHUGHVLJQ

In the AS7C181026LL design, priority was placed on low power, while maintaining moderately high performance. To reduce standby and

data retention current, a 6-transistor memory cell was utilized. Active power was reduced considerably over traditional designs by using

Intelliwatt™ power reduction circuitry. With Intelliwatt™, SRAM powers down unused circuits between access operations, providing

incremental power savings. During periods of inactivity, Intelliwatt™ SRAM power consumption approaches fully deactivated standby

power, even though the chip is enabled. This power savings, both in active and inactive modes, results in longer battery life, and better

system marketability. All chip inputs and outputs are TTL-compatible, and operation is from a single power supply.

$EVROXWHPD[LPXPUDWLQJV

Parameter

Voltage on any input pin relative to

Voltabe on any I/O pin

Power dissipation

Storage temperature (plastic)

DC output current

Symbol

tIN

tI/O

stg

out

Min

–1

–

–55

–

Max

+2.5

+ 0.5

1.0

+150

Unit

NOTE: Stresses greater than those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

$//,$1&(6(0,&21'8&725

',' %

3UHOLPLQDU\LQIRUPDWLRQ

$6&//

7UXWKWDEOH

I/O0–I/O7

High Z

OUT

High Z

OUT

High Z

I/O8–I/O15

High Z

OUT

High Z

Mode

Standby, power down

Read I/O0–I/O7

Read I/O8–I/O15

Read I/O0–I/O15

Write I/O0–I/O15

Write I/O0–I/O7

Write I/O8–I/O15

Output disable

Disable, power down

65$0

Key: X = don’t care, L = Low, H = High

5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV

Parameter

Supply voltage

Input voltage

Ambient operating temperature

†

Symbol

Commercial

Industrial

Min

1.65

0.0

0.7 × V

–0.5

†

-40

Typ

1.80

0.0

–

Max

1.95

0.0

+ 0.5

0.3 × V

Unit

°C

min = –3.0V for pulse width less than 10 ns.

'&RSHUDWLQJFKDUDFWHULVWLFV

-55*

Parameter

Input leakage

current

Symbol

Test conditions

≤

Outputs disabled,

≤

out

≤

, V

= Max,

f = f

Max

= 1/t

RC,

OUT

= 0

, V

= Max, f = 0,

OUT

= 0

≥

, V

= Max,

f = f

Max

= 1/t

≥

–0.2V, V

Max,

≤

+ 0.2V or

≥

- 0.2V, f = 0

= 100 µA, V

= Min

= –100 µA, V

= Min

–

Min

–

Max

–

Min

–

-70

Max

–

-100

Min

–

Max

Unit

µA

Output leakage

current

Operating

power supply

current

DD1

SB1

Standby

power supply

current

–

0.8×V

0.2

–

0.8×V

0.2

–

0.8×V

0.2

–

µA

Output voltage

*For availability of 55 ns device, contact Alliance.

',' %

$//,$1&(6(0,&21'8&725

$6&//

3UHOLPLQDU\LQIRUPDWLRQ

&DSDFLWDQFH

Parameter

Input capacitance

I/O capacitance

Outputs disabled in all cases.

= worst case power consumption.

= current for the disabled, bus-active condition.

CC1

= enabled, bus-inactive condition.

SB1

= “full standby” or the disabled, bus-inactive condition.

CCDR

= current in data retention (reduced VDD) mode.

¦ 0+]7

Symbol

I/O

Signals

A, CE, WE, OE, LB, UB

I/O

Test conditions

= 0V

= V

out

= 0V

Max Unit

65$0

5HDGF\FOH

55*

Parameter

Read cycle time

Address access time

Chip enable access time

Output enable (OE) access time

Output hold from address change

Chip enable Low to output in Low Z

Chip enable High to output in High Z

OE Low to output in Low Z

OE High to output in High Z

Byte select access time

Byte select Low to Low-Z

Byte select High to High-Z

Power up time

Power down time

*For availability of 55 ns device, contact Alliance.

Max

–

Min

–

Max

–

Min

100

–

100

Max

–

100

–

Unit

4,5

4, 5, 12

4, 5

3, 12

Notes

Symbol

ACE

CLZ

CHZ

OLZ

OHZ

BLZ

BHZ

Min

–

.H\WRVZLWFKLQJZDYHIRUPV

Rising input

Falling input

Undefined output/don’t care

5HDGZDYHIRUP

6,7,9

Address

Data out

Previous data valid

Data valid

$//,$1&(6(0,&21'8&725

',' %

3UHOLPLQDU\LQIRUPDWLRQ

$6&//

5HDGZDYHIRUP

6,8,9

Address

OLZ

LB, UB

BLZ

Data out

Data valid

BHZ

ACE

OHZ

65$0

:ULWHF\FOH

55*

Parameter

Write cycle time

Chip enable to write end

Address setup to write end

Address setup time

Write pulse width

Address hold from end of write

Data valid to write end

Data hold time

Write enable to output in High Z

Output active from write end

Byte Select low to end of write

*For availability of 55 ns device, contact Alliance.

Max

–

Min

–

Max

–

Min

100

–

100

Max

–

Unit

4, 5

Notes

Symbol

Min

–

:ULWHZDYHIRUP

10,11

Address

LB, UB

Data in

Data out

',' %

Data valid

HI-Z

Data undefined

$//,$1&(6(0,&21'8&725

参数对比

与AS7C181026LL-55BC相近的元器件有：AS7C181026LL-100TI、AS7C181026LL-70BC、AS7C181026LL-70TI、AS7C181026LL-55TC、AS7C181026LL-70TC、AS7C181026LL-55TI、AS7C181026LL-70BI、AS7C181026LL-55BI、AS7C181026LL-100TC。描述及对比如下：

型号	AS7C181026LL-55BC	AS7C181026LL-100TI	AS7C181026LL-70BC	AS7C181026LL-70TI	AS7C181026LL-55TC	AS7C181026LL-70TC	AS7C181026LL-55TI	AS7C181026LL-70BI	AS7C181026LL-55BI	AS7C181026LL-100TC
描述	Standard SRAM, 64KX16, 55ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, CSP, BGA-48	Standard SRAM, 64KX16, 100ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44	Standard SRAM, 64KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, CSP, BGA-48	Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44	Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44	Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44	Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44	Standard SRAM, 64KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, CSP, BGA-48	Standard SRAM, 64KX16, 55ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, CSP, BGA-48	Standard SRAM, 64KX16, 100ns, CMOS, PDSO44, 18.4 X 10.2 MM, TSOP2-44
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	BGA	TSOP2	BGA	TSOP2	TSOP2	TSOP2	TSOP2	BGA	BGA	TSOP2
包装说明	BGA, BGA48,6X8,30	SOP, TSOP44,.46,32	BGA, BGA48,6X8,30	SOP, TSOP44,.46,32	SOP, TSOP44,.46,32	SOP, TSOP44,.46,32	SOP, TSOP44,.46,32	BGA, BGA48,6X8,30	BGA, BGA48,6X8,30	SOP, TSOP44,.46,32
针数	48	44	48	44	44	44	44	48	48	44
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	55 ns	100 ns	70 ns	70 ns	55 ns	70 ns	55 ns	70 ns	55 ns	100 ns
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B48	R-PDSO-G44	R-PBGA-B48	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44	R-PBGA-B48	R-PBGA-B48	R-PDSO-G44
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
内存密度	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	16	16	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	48	44	48	44	44	44	44	48	48	44
字数	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words
字数代码	64000	64000	64000	64000	64000	64000	64000	64000	64000	64000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	85 °C	70 °C	85 °C	70 °C	70 °C	85 °C	85 °C	85 °C	70 °C
组织	64KX16	64KX16	64KX16	64KX16	64KX16	64KX16	64KX16	64KX16	64KX16	64KX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	SOP	BGA	SOP	SOP	SOP	SOP	BGA	BGA	SOP
封装等效代码	BGA48,6X8,30	TSOP44,.46,32	BGA48,6X8,30	TSOP44,.46,32	TSOP44,.46,32	TSOP44,.46,32	TSOP44,.46,32	BGA48,6X8,30	BGA48,6X8,30	TSOP44,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY	SMALL OUTLINE	GRID ARRAY	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	GRID ARRAY	GRID ARRAY	SMALL OUTLINE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	240	NOT SPECIFIED	240	240	240	240	NOT SPECIFIED	NOT SPECIFIED	240
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大待机电流	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A	4e-7 A
最小待机电流	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
最大压摆率	0.019 mA	0.01 mA	0.015 mA	0.015 mA	0.019 mA	0.015 mA	0.019 mA	0.015 mA	0.019 mA	0.01 mA
最大供电电压 (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
最小供电电压 (Vsup)	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	BALL	GULL WING	BALL	GULL WING	GULL WING	GULL WING	GULL WING	BALL	BALL	GULL WING
端子节距	0.75 mm	0.8 mm	0.75 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.75 mm	0.75 mm	0.8 mm
端子位置	BOTTOM	DUAL	BOTTOM	DUAL	DUAL	DUAL	DUAL	BOTTOM	BOTTOM	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
厂商名称	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	-	-	-	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]