November 2004
®
AS7C332MNTF18A
3.3V 2M x 18 Flowthrough SRAM with NTD
TM
Features
•
•
•
•
•
•
•
•
•
Organization: 2,097,152 words × 18 bits
NTD
™
architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP and 165-ball BGA package
Byte write enables
•
•
•
•
•
•
•
•
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Boundary Scan using IEEE 1149.1 JTAG function is avail-
able in 165 Ball BGA Package only.
Logic block diagram
A[19:0]
20
D
Address
register
burst logic
Q
20
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
CLK
D
Q
20
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
2M x 18
SRAM
array
DQ [a,b]
18
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
325
140
90
-85
10
8.5
300
130
90
-10
12
10
375
130
90
Units
ns
ns
mA
mA
mA
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Alliance Semiconductor
P. 1 of 26
Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MNTF18A
®
32 Mb Synchronous SRAM products list
1,2
Org
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
Part Number
AS7C332MPFS18A
AS7C331MPFS32A
AS7C331MPFS36A
AS7C332MPFD18A
AS7C331MPFD32A
AS7C331MPFD36A
AS7C332MFT18A
AS7C331MFT32A
AS7C331MFT36A
AS7C332MNTD18A
AS7C331MNTD32A
AS7C331MNTD36A
AS7C332MNTF18A
AS7C331MNTF32A
AS7C331MNTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
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P. 2 of 26
AS7C332MNTF18A
®
100-pin TQFP - top view
100
99
98
97
96
95
94
93
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
V
SS
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQPa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
11/25/04, v 1.1
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
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P. 3 of 26
AS7C332MNTF18A
®
Pin and ball assignment
165-ball BGA - top view
1
NC
A
NC
B
NC
C
NC
D
NC
E
NC
F
NC
G
H
J
DQb
K
DQb
L
DQb
M
DQPb
N
NC
P
LBO
R
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is
desired.
A
A
A
TMS
A0
1
TCK
A
A
A
A
NC
NC
NC
NC
NC
V
SS
DQb
NC
NC
DQb
DQb
DQb
DQb
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
CE1
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
1
R/W
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
2
A
3
CE0
4
BWb
5
NC
6
CE2
7
CEN
8
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
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AS7C332MNTF18A
®
Functional Description
The AS7C332MNTF18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM)
organized as 2,097,152 words × 18 bits and incorporates a LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD
™
, write and read operations can be used in any order without producing dead bus cycle.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C332MNTF18A operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate
power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package and
165 BGA Ball Grid Array package.
Capacitance
Parameter
Input capacitance
I/O capacitance
*Guaranteed not tested
Symbol
C
IN*
C
I/O*
I/O pins
Signals
Address and control pins
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1
This parameter is sampled.
Symbol
1 layer
4 layer
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
11/25/04, v 1.1
Alliance Semiconductor
P. 5 of 26
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