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AS7C332MPFS18A-166TQC

3.3V 2M x 18 pipelined burst synchronous SRAM

器件类别：存储    存储   

厂商名称：ALSC [Alliance Semiconductor Corporation]

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参数 预览 参数对比
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
ALSC [Alliance Semiconductor Corporation]
零件包装代码
QFP
包装说明
LQFP,
针数
100
Reach Compliance Code
unknow
ECCN代码
3A991.B.2.A
最长访问时间
3.5 ns
其他特性
PIPELINED ARCHITECTURE
JESD-30 代码
R-PQFP-G100
JESD-609代码
e0
长度
20 mm
内存密度
37748736 bi
内存集成电路类型
STANDARD SRAM
内存宽度
18
功能数量
1
端子数量
100
字数
2097152 words
字数代码
2000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
2MX18
封装主体材料
PLASTIC/EPOXY
封装代码
LQFP
封装形状
RECTANGULAR
封装形式
FLATPACK, LOW PROFILE
并行/串行
PARALLEL
峰值回流温度（摄氏度）
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
1.6 mm
最大供电电压 (Vsup)
3.465 V
最小供电电压 (Vsup)
3.135 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
TIN LEAD
端子形式
GULL WING
端子节距
0.65 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
文档预览
December 2004
®
AS7C332MPFS18A
3.3V 2M
×
18 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
Organization: 2,097,152 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.1/3.5/3.8 ns
Fast OE access time: 3.1/3.5/3.8 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
•
•
•
•
•
•
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[20:0]
CLK
CS
CLR
Burst logic
Q
21
CS
Address
D
21
19 21
2M x 18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
CLK
D
registers
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.1
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
12/23/04, v.1.5
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MPFS18A
®
32 Mb Synchronous SRAM products list
1,2
Org
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
Part Number
AS7C332MPFS18A
AS7C331MPFS32A
AS7C331MPFS36A
AS7C332MPFD18A
AS7C331MPFD32A
AS7C331MPFD36A
AS7C332MFT18A
AS7C331MFT32A
AS7C331MFT36A
AS7C332MNTD18A
AS7C331MNTD32A
AS7C331MNTD36A
AS7C332MNTF18A
AS7C331MNTF32A
AS7C331MNTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
12/23/04, v.1.5
Alliance Semiconductor
2 of 19
AS7C332MPFS18A
®
Pin assignment
100-pin TQFP - top view
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQPa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
12/23/04, v.1.5
LBO
A
A
A
A
A1
A0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Alliance Semiconductor
3 of 19
AS7C332MPFS18A
®
Functional description
The AS7C332MPFS18A is a high-performance CMOS 32-Mbit Synchronous Static Random Access Memory (SRAM) device
organized as 2,097,152 words × 18 bits. It incorporates a two-stage register-register pipeline for highest frequency on any given
technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
CD
) of 3.1/3.5/3.8 ns enable 200,166 and 133MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
LBO
input.
With
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
LBO
driven low, the device
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes
may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in single-
cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C332MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at
2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
I/O capacitance
* Guaranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
IN
= 0V
V
OUT
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
12/23/04,
v.1.5
Alliance Semiconductor
4 of 19
AS7C332MPFS18A
®
Signal descriptions
Pin
CLK
A,A0,A1
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
ZZ
NC
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
-
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Description
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write
enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
12/23/04, v.1.5
Alliance Semiconductor
5 of 19
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参数对比
与AS7C332MPFS18A-166TQC相近的元器件有：AS7C332MPFS18A、AS7C332MPFS18A-133TQC、AS7C332MPFS18A-133TQCN、AS7C332MPFS18A-133TQI、AS7C332MPFS18A-166TQCN、AS7C332MPFS18A-166TQI、AS7C332MPFS18A-200TQC、AS7C332MPFS18A-200TQI、AS7C332MPFS18A-200TQIN。描述及对比如下：
型号 AS7C332MPFS18A-166TQC AS7C332MPFS18A AS7C332MPFS18A-133TQC AS7C332MPFS18A-133TQCN AS7C332MPFS18A-133TQI AS7C332MPFS18A-166TQCN AS7C332MPFS18A-166TQI AS7C332MPFS18A-200TQC AS7C332MPFS18A-200TQI AS7C332MPFS18A-200TQIN
描述 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM 3.3V 2M x 18 pipelined burst synchronous SRAM
是否Rohs认证 不符合 - 不符合 符合 不符合 符合 不符合 不符合 不符合 符合
厂商名称 ALSC [Alliance Semiconductor Corporation] - ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation]
零件包装代码 QFP - QFP QFP QFP QFP QFP QFP QFP QFP
包装说明 LQFP, - LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, LQFP, LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87
针数 100 - 100 100 100 100 100 100 100 100
Reach Compliance Code unknow - unknow unknow unknow unknow unknow unknow unknow unknow
ECCN代码 3A991.B.2.A - 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
最长访问时间 3.5 ns - 3.8 ns 3.8 ns 3.8 ns 3.5 ns 3.5 ns 3.1 ns 3.1 ns 3.1 ns
其他特性 PIPELINED ARCHITECTURE - PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
JESD-30 代码 R-PQFP-G100 - R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
JESD-609代码 e0 - e0 e3 e0 e3 e0 e0 e0 e3
长度 20 mm - 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm
内存密度 37748736 bi - 37748736 bi 37748736 bi 37748736 bi 37748736 bi 37748736 bi 37748736 bi 37748736 bi 37748736 bi
内存集成电路类型 STANDARD SRAM - STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
内存宽度 18 - 18 18 18 18 18 18 18 18
功能数量 1 - 1 1 1 1 1 1 1 1
端子数量 100 - 100 100 100 100 100 100 100 100
字数 2097152 words - 2097152 words 2097152 words 2097152 words 2097152 words 2097152 words 2097152 words 2097152 words 2097152 words
字数代码 2000000 - 2000000 2000000 2000000 2000000 2000000 2000000 2000000 2000000
工作模式 SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C - 70 °C 70 °C 85 °C 70 °C 85 °C 70 °C 85 °C 85 °C
组织 2MX18 - 2MX18 2MX18 2MX18 2MX18 2MX18 2MX18 2MX18 2MX18
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 LQFP - LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP
封装形状 RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK, LOW PROFILE - FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
并行/串行 PARALLEL - PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度（摄氏度） NOT SPECIFIED - NOT SPECIFIED 245 NOT SPECIFIED 245 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 245
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.6 mm - 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
最大供电电压 (Vsup) 3.465 V - 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
最小供电电压 (Vsup) 3.135 V - 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES - YES YES YES YES YES YES YES YES
技术 CMOS - CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL - COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL
端子面层 TIN LEAD - Tin/Lead (Sn/Pb) MATTE TIN Tin/Lead (Sn/Pb) MATTE TIN TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) MATTE TIN
端子形式 GULL WING - GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.65 mm - 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 QUAD - QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
处于峰值回流温度下的最长时间 NOT SPECIFIED - NOT SPECIFIED 30 NOT SPECIFIED 30 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 30
宽度 14 mm - 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
最大时钟频率 (fCLK) - - 133 MHz 133 MHz 133 MHz - - 200 MHz 200 MHz 200 MHz
I/O 类型 - - COMMON COMMON COMMON - - COMMON COMMON COMMON
输出特性 - - 3-STATE 3-STATE 3-STATE - - 3-STATE 3-STATE 3-STATE
封装等效代码 - - QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 - - QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87
电源 - - 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V - - 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
最大待机电流 - - 0.06 A 0.06 A 0.06 A - - 0.06 A 0.06 A 0.06 A
最小待机电流 - - 3.14 V 3.14 V 3.14 V - - 3.14 V 3.14 V 3.14 V
最大压摆率 - - 0.325 mA 0.325 mA 0.325 mA - - 0.4 mA 0.4 mA 0.4 mA
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JackIeLc 测试/测量
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发书了！经典电路分析设计 DS18B20问题 想实现基于485芯片的多机通信，突然就不行了 STM32W有本新书了 刚买了 mini 2440，大家推荐相关嵌入式经典书籍和网络资料或视频下载地址 极寒与酷热中的秘密揭晓-高低温试验箱探索材料的表现 参赛时用的DDS之类的芯片可以直接买模块吗？ 嵌入式C编程语言入门与深入 F7评测④——串口打印数据 【藏书阁】图表细说电子元器件
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