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AS7C34098A-20JCNTR

SRAM 4M, 3.3V, 20ns, FAST 256K x 16 Asyn SRAM

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厂商名称:Alliance Memory

器件标准:

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
SOJ
包装说明
SOJ,
针数
44
Reach Compliance Code
compliant
Factory Lead Time
10 weeks
最长访问时间
20 ns
JESD-30 代码
R-PDSO-J44
JESD-609代码
e3/e6
长度
28.575 mm
内存密度
4194304 bit
内存集成电路类型
STANDARD SRAM
内存宽度
16
功能数量
1
端子数量
44
字数
262144 words
字数代码
256000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
256KX16
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
245
座面最大高度
3.7592 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
PURE MATTE TIN/TIN BISMUTH
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
10.16 mm
Base Number Matches
1
文档预览
August 2004
®
AS7C34098A
3.3 V 256 K × 16 CMOS SRAM
Features
• Pin compatible with AS7C34098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• JEDEC standard packages
- 44-pin SOJ -400-mil
- 44-pin TSOP 2
- 48-pin Mini BGA
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
- 28.8 mW /max CMOS
• Individual byte read/write controls
Logic block diagram
Pin arrangement for SOJ
and TSOP 2
Bottom View 48BGA
Selection guide
–10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Industrial
Commercial
10
4
180
170
8
–12
12
5
160
150
8
–15
15
6
140
130
8
–20
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
11/14/11, v. 2.2
Alliance Memory Inc.
P. 1 of 11
Copyright © Alliance Memory Inc. All rights reserved.
AS7C34098A
®
Functional description
The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 4/5/6/7 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is
available in the JEDEC standard 400-mil, 44-pin SOJ, TSOP 2.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–65
–55
Max
+5.0
V
CC
+0.50
1.5
+150
+125
±20
Unit
V
V
W
°C
°C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
WE
X
H
X
OE
X
H
X
LB
X
X
H
L
L
H
L
H
L
L
L
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
X
High Z
H
H
L
L
H
L
L
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Write (I
CC
)
Read (I
CC
)
High Z
Output disable (I
CC
)
I/O1–I/O8
High Z
I/O9–I/O16
High Z
Mode
Standby (I
SB
, I
SB1
)
11/14/11,v. 2.2
Alliance Memory Inc
P. 2 of 11
AS7C34098A
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
commercial
industrial
Symbol
V
CC
(10/12/15/20)
V
IH**
V
IL*
T
A
T
A
Min Typical
3.0
2.0
–0.5
0
–40
3.3
Max
3.6
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
°C
°C
* V min = –1.0V for pulse width less than 5ns.
IL
*
V
IH
max = V
CC
+ 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)
1
–10
Parameter
Input leakage
current
Output leakage
current
Operating
power supply
current
Symbol
|I
LI
|
Test conditions
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max
CE = V
IH
or OE = V
IH
or WE = V
IL
V
I/O
= GND to V
CC
V
CC
= Max
CE
V
IL
, f = f
max
I
OUT
= 0mA
V
CC
= Max
CE ≥ V
IH
, f = Max
V
CC
= Max
CE ≥ V
CC
– 0.2V, V
IN
≥ V
CC
– 0.2V or
V
IN
≤ 0.2V, f = 0
Output voltage
V
OL
V
OH
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
2.4
0.4
2.4
0.4
2.4
0.4
2.4
0.4
V
V
Industrial
Commercial
–12
–15
–20
Min Max Min Max Min Max Min Max Unit
1
1
1
1
µA
|I
LO
|
-
1
-
1
-
1
-
1
µA
180
170
60
160
150
60
140
130
60
110 mA
100 mA
60
mA
I
CC
I
SB
Standby power
supply current
I
SB1
8
8
8
8
mA
Capacitance (f = 1MHz, T
a
= 25° C, V
CC
= NOMINAL)
2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE, UB, LB
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
6
8
Unit
pF
pF
11/14/11,v. 2.2
Alliance Memory Inc
P. 3 of 11
AS7C34098A
®
Read cycle (over the operating range)
3,9
–10
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
LB, UB access time
LB, UB Low to output in low Z
LB, UB High to output in high Z
Power up time
Power down time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
BA
t
BLZ
t
BHZ
t
PU
t
PD
Min
10
3
3
0
0
0
Max
10
10
4
5
5
5
5
10
12
3
3
0
0
0
–12
Min
Max
12
12
5
6
6
6
6
12
15
3
3
0
0
0
–15
Min
Max
15
15
6
7
7
7
7
15
20
3
3
0
0
0
–20
Min
Max
20
20
7
9
9
8
9
20
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
4, 5
4, 5
4, 5
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
6,7,9
t
RC
Address
t
OH
Data
OUT
Previous data valid
t
AA
Data valid
t
OH
11/14/11,v. 2.2
Alliance Memory Inc
P. 4 of 11
AS7C34098A
®
Read waveform 2 (CE, OE, UB, LB controlled)
6,8,9
t
RC
Address
t
AA
OE
t
OE
t
OLZ
CE
t
ACE
t
CLZ
LB, UB
t
BA
t
BLZ
Data
OUT
Data valid
t
BHZ
t
CHZ
t
OHZ
t
OH
Write cycle (over the operating range)
10
–10
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width (OE = High)
Write pulse width (OE = Low)
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in High-Z
Output active from write end
Byte enable Low to write end
Symbol Min
t
WC
t
CW
t
AW
t
AS
t
WP1
t
WP2
t
WR
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
10
7
7
0
7
10
0
0
5
0
0
3
7
Max
5
12
8
8
0
8
12
0
0
6
0
0
3
8
6
–12
Min
Max
Min
15
10
10
0
10
15
0
0
7
0
0
3
10
–15
Max
7
Min
20
12
12
0
12
20
0
0
9
0
0
3
12
–20
Max
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
Note
11/14/11,v. 2.2
Alliance Memory Inc
P. 5 of 11
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