The ASM3P2508A allows significant system cost savings
by reducing the number of circuit board layers and
shielding that are required to pass EMI regulations. The
ASM3P2508A modulates the output of PLL in order to
spread the bandwidth of a synthesized clock, thereby
decreasing the peak amplitudes of its harmonics. This
results in significantly lower system EMI compared to the
typical narrow band signal produced by oscillators and
most clock generators. Lowering EMI by increasing a
signal’s bandwidth is called spread spectrum clock
generation.
The ASM3P2508A has a feature to power down the
72MHz/48MHz output by writing data into specific
registers in the device via I2C. By writing a ‘0’ into bit 1 of
Byte 0, the PLL block generating 72 MHz / 48MHz can be
powered down. Writing ‘0’ into bit ‘7’ of Byte 1 selects an
output of 72 MHz on FOUT2CLK while a ‘1’ at the same
Product Description
The ASM3P2508A is a versatile spread spectrum
frequency
modulator.
The
ASM3P2508A
reduces
electromagnetic interference (EMI) at the clock source.
location selects a 48 MHz clock output. However, the I2C
block, crystal oscillator, and the PLL block generating
120MHz would be always running.
Block Diagram
V
DD
XIN
XOUT
Crystal
Oscillator
PLL 1
FOUT1CLK
(120 MHz)
SCL
SDA
I2C
Interface
PLL 2
FOUT2CLK
(72 MHz / 48 MHz)
V
SS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara CA
•
Tel: 408-855-4900
•
Fax: 408-855-4999
•
www.alsc.com
February 2005
rev 1.3
Pin Configuration
XIN
XOUT
V
DD
FOUT1CLK
1
2
8
7
ASM3P2508A
V
SS
SCL
SDA
FOUT2CLK
ASM3P2508A
3
4
6
5
Pin Description
Pin Name
XIN
XOUT
V
DD
FOUT1CLK
FOUT2CLK
SDA
SCL
V
SS
Type
I
O
P
O
O
I/O
I
P
Connection to crystal
Connection to crystal
Description
Power supply for the analog and digital blocks
Clock output-1 (120 MHz) - default
Clock output-2 ( 72 MHz / 48 MHz)
I2C Data
I2C Clock
Ground to entire chip
Peak EMI Reducing Solution
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February 2005
rev 1.3
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
ASM3P2508A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
Supply Voltage
Ambient Operating
Temperature Range
Crystal Resonator
Frequency
Serial Data Transfer
Rate
Output Driver Load
Capacitance
Symbol
V
DD
T
A
F
XIN
Condition /
Description
3.3V ± 10%
Min
3
-10
Typ
3.3
Max
3.6
+70
14.31818
Unit
V
°C
MHz
Standard Mode
C
L
10
100
15
Kb/s
pF
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February 2005
rev 1.3
DC Electrical Characteristics
(Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated)
ASM3P2508A
Parameter
Overall
Supply Current,
Dynamic
Supply Current,
Static
All input pins
Symbol
Conditions / Description
Min
Typ
Max
Unit
I
cc
I
DD
V
DD
=3.3V, F
CLK
=14.31818MHz,
C
L
=15pF
V
DD
= 3.3V, Software Power Down*
40
27
49
35
60
43
mA
mA
High-Level Input
V
DD
=3.3V
V
IH
Voltage
Low-Level Input
V
DD
=3.3V
V
IL
Voltage
High-Level Input
I
IH
Current
Low-Level Input
I
IL
Current (pull-up)
Clock Outputs (FOUT1CLK, FOUT2CLK)
High-Level Output
Voltage
Low-Level Output
Voltage
Output Impedance
V
OH
V
OL
Z
OH
Z
OL
V
DD
= 3.3V, I
OH
= 20mA
V
DD
= 3.3V, I
OL
= 20mA
V
O
=0.5V
DD
; output driving high
Vo=0.5V
DD
; output driving low
2.0
V
SS
-0.3
-1
-20
-
-
-
-36
V
DD
+0.3
0.8
1
-80
V
V
µ
A
µ
A
V
V
2.5
0
-
-
-
-
29
27
3.3
0.4
-
-
* FOUT1CLK (120MHz) is functional and not loaded
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February 2005
rev 1.3
AC Electrical Characteristics
Parameter
Rise Time
Fall Time
Clock Duty
Cycle
Frequency
Deviation
Jitter, Long
Term
ASM3P2508A
Symbol
t
r
t
f
t
D
f
D
Conditions/ Description
FOUT1CLK
FOUT2CLK
FOUT1CLK
V
O
= 2.0V to 0.8V; C
L
= 15pF
FOUT2CLK
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
V
O
= 0.8V to 2.0V; C
L
= 15pF
Output Frequency =120MHz
Output Frequency =72MHz /48 MHz
On rising edges 500 uS apart at 2.5 V relative to an
ideal clock, PLL B inactive *
On rising edges 500 uS apart at 2.5 V relative to an
