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ASM3I2769AF-08ST

Clock Generator, 13MHz, CMOS, PDSO8, ROHS COMPLIANT, SOIC-8

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:ALSC [Alliance Semiconductor Corporation]

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
零件包装代码
SOIC
包装说明
SOP,
针数
8
Reach Compliance Code
unknown
ECCN代码
EAR99
其他特性
ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码
R-PDSO-G8
JESD-609代码
e3
长度
4.9 mm
端子数量
8
最高工作温度
85 °C
最低工作温度
-40 °C
最大输出时钟频率
13 MHz
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
250
主时钟/晶体标称频率
13 MHz
认证状态
Not Qualified
座面最大高度
1.75 mm
最大供电电压
3.6 V
最小供电电压
2.7 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Matte Tin (Sn)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
3.91 mm
uPs/uCs/外围集成电路类型
CLOCK GENERATOR, OTHER
Base Number Matches
1
文档预览
September 2005
rev 1.8
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V / 2.5V Supply
Operating current less than 4mA.
Low power CMOS design.
Input frequency range: 6MHz to 12MHz for 2.5V.
: 6MHz to 13MHz for 3.3V.
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: ±1% @ 10MHz
Available in 6 pin TSOT-23, 8 pin SOIC and
8 pin TSSOP Packages.
ASM3P2769A
The ASM3P2769A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2769A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2769A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Product Description
The ASM3P2769A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2769A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of
all clock
dependent signals. The ASM3P2769A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency Deviation
Specification
VDD = 3.3V / 2.5V
200pS (Max)
45/55%
F
IN
/256
±1% @ 10MHz
Block Diagram
VDD
PD
XIN
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Modulation
PLL
XOUT
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
September 2005
rev 1. 8
Pin Configuration (6-pin TSOT-23 Package)
ASM3P2769A
PD
1
XOUT
2
6
VSS
ModOUT
VDD
ASM3P2769A
5
4
XIN/CLKIN
3
Pin Description
Pin#
1
2
3
4
5
6
Pin Name
PD
XOUT
XIN/CLKIN
VDD
ModOUT
VSS
Type
I
O
I
P
O
P
Description
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used.
Crystal connection. If using an external reference, this pin must be left unconnected.
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Power supply for the entire chip.
Spread spectrum clock output.
Ground connection.
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
2 of 12
September 2005
rev 1. 8
Pin Configuration (8-pin SOIC and TSSOP Packages)
ASM3P2769A
XIN/CLKIN
1
XOUT
2
8
7
6
5
VDD
NC
ModOUT
VSS
ASM3P2769A
PD
3
NC
4
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
PD
NC
VSS
ModOUT
NC
VDD
Type
I
O
I
-
P
O
-
P
Description
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used.
No connect.
Ground connection.
Spread spectrum clock output.
No connect.
Power supply for the entire chip.
Modulation Profile
Specification
Description
Frequency
Range
For 2.5V Supply
For 3.3V Supply
Modulation Equation
Frequency Deviation
Specification
6MHz < CLKIN < 12MHz
6MHz < CLKIN < 13MHz
F
IN
/256
±1% @ 10MHz
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
3 of 12
September 2005
rev 1. 8
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
ASM3P2769A
Parameter
Rating
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
°C
°C
°C
°C
KV
Voltage on any pin with respect to Ground
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics for 2.5V Supply
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Parameter
Min
VSS-0.3
2.0
-
-
-
-
-
1.8
-
-
2.375
-
-
Typ
-
-
-
-
3
3
-
-
-
2.5
2.5
-
50
Max
0.8
VDD+0.3
-35
35
-
-
0.6
-
10
-
2.625
5
-
Unit
V
V
µA
µA
mA
mA
V
V
µA
mA
V
mS
XOUT output low current (@0.5V, VDD=2.5V)
XOUT output high current (@1.8V, VDD=2.5V)
Output low voltage (VDD = 2.5 V, I
OL
= 8mA)
Output high voltage (VDD = 2.5 V, I
OH
= 8mA)
Static supply current *
Dynamic supply current (2.5V, 10MHz and with no load)
Operating Voltage
Power-up time(first locked cycle after power up)**
Output impedance
* XIN/CLKIN pin and PD pin are pulled low
** V
DD
and XIN/CLKIN input are stable; PD pin is made high from low.
AC Electrical Characteristics for 2.5V Supply
Symbol
CLKIN
ModOUT
f
d
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output frequency
Frequency Deviation
Input Frequency = 6MHz
Input Frequency = 12MHz
Parameter
Min
6
6
-
-
0.6
0.4
-
45
Typ
-
-
±1.55
±0.8
1.2
0.9
-
50
Max
12
12
-
-
1.5
1.1
200
55
Unit
MHz
MHz
%
nS
nS
pS
%
Output rise time (measured at 0.7V to 1.7V)
Output fall time (measured at 1.7V to 0.7V)
Jitter (cycle to cycle)
Output duty cycle
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
4 of 12
September 2005
rev 1. 8
DC Electrical Characteristics for 3.3V Supply
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated).
ASM3P2769A
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Parameter
Min
VSS - 0.3
2.0
-
-
-
-
-
2.5
-
-
2.7
-
-
Typ
-
-
-
-
3
3
-
-
-
3.5
3.3
-
45
Max
0.8
VDD + 0.3
-35
35
-
-
0.4
-
10
-
3.6
5
-
Unit
V
V
µA
µA
mA
mA
V
V
µA
mA
V
mS
XOUT output low current (@0.4V, VDD=3.3V)
XOUT output high current (@2.5V, VDD=3.3V)
Output low voltage (VDD = 3.3 V, I
OL
= 8mA)
Output high voltage (VDD = 3.3 V, I
OH
= 8mA)
Static supply current *
Dynamic supply current (3.3V, 10MHz and with no load)
Operating Voltage
Power-up time(first locked cycle after power up)**
Output impedance
* XIN/CLKIN pin and PD pin are pulled low
** V
DD
and XIN/CLKIN input are stable, PD pin is made high from low.
AC Electrical Characteristics for 3.3V Supply
Symbol
CLKIN
ModOUT
f
d
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output frequency
Frequency Deviation
Input Frequency = 6MHz
Input Frequency = 13MHz
Parameter
Min
6
6
-
-
0.4
0.3
-
45
Typ
-
-
±1.55
±0.75
1.2
0.9
-
50
Max
13
13
-
-
1.4
1.1
200
55
Unit
MHz
MHz
%
nS
nS
pS
%
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
5 of 12
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