ASM3P2811A/B,
ASM3P2812A/B,
ASM3P2814A/B
Low Power EMI Reduction IC
Description
The ASM3P28XX devices are versatile spread spectrum frequency
modulators designed specifically for a wide range of input clock
frequencies from 10 MHz to 40 MHz. Refer to
Input/Output
Frequency Range Selection Table.
The ASM3P28XX can generate an
EMI reduced clock from crystal, ceramic resonator, or system clock.
The ASM3P28XX−A and the ASM3P28XX−B offer various
combinations of spread options and percentage deviations. Refer to
Frequency Deviation and Spread Selection Table.
These combinations
include Down and Center Spread, and percentage deviation range
from
±0.625%
to
−3.5%.
The ASM3P28XX reduces electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. The ASM3P28XX allows
significant system cost savings by reducing the number of circuit
board layers, ferrite beads, shielding, and other passive components
that are traditionally required to pass EMI regulations.
The ASM3P28XX modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
The ASM3P28XX uses the most efficient and optimized
modulation profile approved by the FCC and is implemented in a
proprietary all−digital method.
Applications
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
XIN / CLKIN
VSS
D_C
SRS
(Top View)
1
XOUT
VDD
FRS
ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
The ASM3P28XX is targeted towards EMI management for memory and LVDS interfaces in mobile graphic chipsets and
high−speed digital applications such as PC peripheral devices, consumer electronics, and embedded controller systems.
Features
•
FCC Approved Method of EMI Attenuation
•
Provides up to 15 dB EMI Reduction
•
Generates a 1x, 2x and 4x Low EMI Spread Spectrum
•
8 Frequency Deviation Selections:
•
•
•
•
•
•
•
♦
Clock of the Input Frequency
♦
1x: ASM3P2811A/B
♦
2x: ASM3P2812A/B
♦
4x: ASM3P2814A/B
•
Optimized for Input Frequency Range from 10 MHz to
40 MHz
•
Internal Loop Filter Minimizes External Components
and Board Space
•
Selectable Spread Options:
♦
Down Spread and Center Spread
±0.625%
to
−3.5%
Low Inherent Cycle−to−Cycle Jitter
3.3 V Operating Voltage
CMOS/TTL Compatible Inputs and Outputs
Pin−out Compatible with Cypress CY25811, CY25812
and CY25814
Commercial and Industrial Temperature Range
Available in 8−pin SOIC and TSSOP Packages
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 3
1
Publication Order Number:
ASM3P2811A/D
ASM3P2811A/B, ASM3P2812A/B, ASM3P2814A/B
D_C
SRS FRS
VDD
PLL
XIN / CLKIN
Crystal
Oscillator
XOUT
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
1
2
3
Pin Name
XIN / CLKIN
VSS
D_C
Type
I
P
I
Description
Crystal connection or external Clock input.
Ground to entire chip.
Digital logic input used to select Down (LOW) or Center (HIGH) spread options.
(Refer to
Frequency Deviation and Spread Selection Table).
This pin has an internal pull−up resistor.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Frequency Deviation and Spread Selection Table).
This pin has an internal pull−up resistor.
Spread spectrum clock output
Frequency range select. Digital logic input used to select Input frequency range
(Refer to
Input/Output Frequency Range Selection Table).
This pin has an internal pull−up resistor.
Power supply for the entire chip.
Crystal connection. If using an external reference, this pin must be left unconnected.
4
SRS
I
5
6
ModOUT
FRS
O
I
7
8
VDD
XOUT
P
O
Table 2. INPUT/OUTPUT FREQUENCY RANGE SELECTION
Part Number
FRS (pin 6)
ASM3P2811 (1x)
Input
(MHz)
0
1
10−20
20−40
Output
(MHz)
10−20
20−40
ASM3P2812 (2x)
Input
(MHz)
10−20
20−40
Output
(MHz)
20−40
40−80
ASM3P2814 (4x)
Input
(MHz)
10−20
20−40
Output
(MHz)
40−80
80−160
Input Frequency / 448
Input Frequency / 896
Modulation Rate
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2
ASM3P2811A/B, ASM3P2812A/B, ASM3P2814A/B
Table 3. OUTPUT FREQUENCY DEVIATION AND SPREAD SELECTION
Frequency Deviation (%)
(Note 1)
FS = 0
Part Number
ASM3P28XXA
D_C (pin 3)
0
0
1
1
ASM3P28XXB
0
0
1
1
SRS (pin 4)
0
1
0
1
0
1
0
1
10/20/40 (MHz)
−3
−3.7
±1.5
±1.8
−1.7
−2.0
±0.75
±1.0
20/40/80 (MHz)
−2.5
−3.4
±1.2
±1.6
−1.0
−1.5
±0.6
±0.75
FS = 1
20/40/80 (MHz)
−2.7
−3.8
±1.5
±1.9
−1.5
−2.0
±0.8
±1.0
40/80/160 (MHz)
−2.6
−3.6
±1.3
±1.8
−1.4
−1.9
±0.7
±0.9
1. Frequency Deviation given in the table is for the Output Frequency Range covering ASM3P2811x / 12x / 14x.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
, V
IN
T
STG
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD 22− A114−B)
Rating
−0.5
to +4.6
−65
to +125
260
150
2
Unit
V
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Symbol
VDD
T
A
C
L
C
IN
Parameter
Voltage on any pin with respect to GND
Operating temperature
Load Capacitance
Input Capacitance
Min
3.0
−40
Max
3.6
+85
10
7
Unit
V
°C
pF
pF
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3
ASM3P2811A/B, ASM3P2812A/B, ASM3P2814A/B
Table 6. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
(Inputs D_C, SRS and FRS are pulled high internally)
Input high current
XOUT Output low current (V
XOL
@ 0.4 V, V
DD
= 3.3 V)
XOUT Output high current (V
XOH
@ 2.5 V, V
DD
= 3.3 V)
Output low voltage (V
DD
= 3.3 V, I
OL
= 5 mA)
Output high voltage (V
DD
= 3.3 V, I
OH
=
−5
mA)
Dynamic supply current (Unloaded Output)
Static supply current, Standby mode (CLKIN pulled to GND)
Operating voltage
Power up time (first locked clock cycle after power up)
Clock out impedance
76
3.0
3.3
2.5
8
18
4.5
3.6
500
Parameter
Min
VSS−0.3
2
Typ
Max
0.8
V
DD
+0.3
−50
50
3
3
0.4
Unit
V
V
mA
mA
mA
mA
V
V
mA
mA
V
mS
W
Table 7. AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
f
OUT
Parameter
Input frequency for ASM3P2811/12/13/14 A/B
Output frequency for ASM3P2811A/B
Output frequency for ASM3P2812A/B
Output frequency for ASM3P2814A/B
t
LH
(Note 2)
t
HL
(Note 2)
t
JC
t
D
Output rise time (measured at 0.8 V to 2.0 V)
Output fall time (measured at 2.0 V to 0.8 V)
Cycle−to−Cycle Jitter (Unloaded Output)
Output duty cycle
45
Min
10
10
20
40
0.5
0.8
0.9
1.0
±250
50
55
Typ
Max
40
40
80
160
1.2
1.3
Unit
MHz
MHz
MHz
MHz
nS
nS
pS
%
2. t
LH
and t
HL
are measured into a capacitive load of 10 pF.
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4
ASM3P2811A/B, ASM3P2812A/B, ASM3P2814A/B
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
A
A1
A2
b
E1
E
c
D
E
E1
e
L
L1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
NOM
MAX
1.20
0.15
0.90
1.05
0.30
0.20
3.00
6.40
4.40
0.65 BSC
1.00 REF
3.10
6.50
4.50
0.50
0.60
0.75
θ
e
0º
8º
TOP VIEW
D
A2
A
q1
c
A1
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
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5
嵌入式系统
