ASM3P622S00B,
ASM3P622S00E
Product Preview
Low Frequency
TIMING SAFEt Peak EMI
Reduction IC
Description
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ASM3P622S00B/E is a versatile, 3.3 V Zero−delay buffer designed
to distribute low frequency Timing−Safe clocks with Peak EMI
reduction. ASM3P622S00B is an eight−pin version, accepts one
reference input and drives out one low−skew Timing−Safe clock.
ASM3P622S00E accepts one reference input and drives out eight
low−skew Timing−Safe clocks.
ASM3P622S00B/E has an SS% that selects 2 different Deviation
and associated Input−Output Skew (TSKEW). Refer to
Spread
Spectrum Control
and
Input−Output Skew
table for details.
ASM3P622S00E has a CLKOUT for adjusting the Input−Output
clock delay, depending upon the value of capacitor connected at this
pin to GND.
ASM3P622S00B/E operates from a 3.3 V supply and is available in
two different packages, as shown in the ordering information table,
over commercial and Industrial temperature range.
Application
TSSOP−8
T SUFFIX
CASE 948AL
SOIC−8
S SUFFIX
CASE 751BD
TSSOP−16
T SUFFIX
CASE 948AN
SOIC−16
S SUFFIX
CASE 751BG
ASM3P622S00B/E is targeted for use in Displays and memory
interface systems.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
•
Low Frequency Clock Distribution with Timing−Safe Peak EMI
•
•
•
•
•
•
•
•
•
Reduction
Input Frequency Range: 4 MHz
−
20 MHz
2 Different Spread Selection Options
Spread Spectrum can be Turned ON/OFF
External Input−Output Delay Control Option
Supply Voltage: 3.3 V
±
0.3 V
Commercial and Industrial Temperature Range
Packaging Information:
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00E: 16 pin SOIC, and TSSOP
The First True Drop−in Solution
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P2
1
Publication Order Number:
ASM3P622S00/D
ASM3P622S00B, ASM3P622S00E
VDD
SS%
DLY_CTRL
CLKIN
CLKOUT(s)*
(Timing−Safe)
PLL
SSON
GND
*For ASM3P622S00E
−
8 CLKOUTS
Figure 1. General Block Diagram
Spread Spectrum Frequency Generation
Zero Delay and Skew Control
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P622S00B/E
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified modulation
rate. With center modulation, the average frequency is the
same as the unmodulated frequency and there is no
performance degradation.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
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ASM3P622S00B, ASM3P622S00E
Pin Configuration for ASM3P622S00B
CLKIN
NC
SS%
GND
1
2
ASM3P622S00B
3
4
8
7
6
5
NC
VDD
CLKOUT
SSON
Table 1. PIN DESCRIPTION FOR ASM3P622S00B
Pin #
1
2
3
4
5
6
7
8
1.
2.
3.
4.
Pin Name
CLKIN (Note 1)
NC
SS% (Note 3)
GND
SSON (Note 3)
CLKOUT (Note 2)
VDD
NC
I
P
I
O
P
Type
I
Description
External reference Clock input , 5 V tolerant input
No Connect
Spread Spectrum Selection. Has an internal pull up resistor
Ground
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum
is enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor.
Buffered clock output (Note 4)
3.3 V supply
No Connect
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
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ASM3P622S00B, ASM3P622S00E
Pin Configuration for ASM3P622S00E
CLKIN
CLKOUT1
VDD
SS%
GND
CLKOUT2
CLKOUT3
DLY_CTRL
1
2
3
4
5
6
7
8
ASM3P622S00E
16
15
14
13
12
11
10
9
CLKOUT
CLKOUT7
CLKOUT6
VDD
GND
CLKOUT5
CLKOUT4
SSON
Table 2. PIN DESCRIPTION FOR ASM3P622S00E
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5.
6.
7.
8.
Pin Name
CLKIN (Note 5)
CLKOUT1 (Note 6)
V
DD
SS% (Note 7)
GND
CLKOUT2 (Note 6)
CLKOUT3 (Note 6)
DLY_CTRL
SSON (Note 7)
CLKOUT4 (Note 6)
CLKOUT5 (Note 6)
GND
V
DD
CLKOUT6 (Note 6)
CLKOUT7 (Note 6)
CLKOUT (Note 6)
Type
I
O
P
I
P
O
O
O
I
O
O
P
P
O
O
O
Description
External reference Clock input, 5 V tolerant input
Buffered clock output (Note 8)
3.3 V supply
Spread Spectrum Selection. Refer to
Spread Spectrum Control
and
Input−Output
Skew Table. Has an internal pull up resistor.
Ground
Buffered clock output (Note 8)
Buffered clock output (Note 8)
External Input−Output Delay control.
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum
is enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor.
Buffered clock output (Note 8)
Buffered clock output (Note 8)
Ground
3.3 V supply
Buffered clock output (Note 8)
Buffered clock output (Note 8)
Buffered clock output (Note 8)
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
Table 3. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE
Device
ASM3P622S00B/E
Input Frequency
12 MHz
SS %
0
1
9. T
SKEW
is measured in units of the Clock Period
Deviation
±0.25
%
±0.50
%
Input−Output Skew (±T
SKEW
)
0.0625 (Note 9)
0.125 (Note 9)
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ASM3P622S00B, ASM3P622S00E
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VIN
T
STG
T
s
T
J
T
DV
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (CLKIN)
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−0.5
to +7
−65
to +125
260
150
2
Unit
V
V
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
−40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage (Note 10)
Input HIGH Voltage (Note 10)
Input LOW Current
Input HIGH Current
Output LOW Voltage (Note 11)
Output HIGH Voltage (Note 11)
Supply Current
Output Impedance
V
IN
= 0 V
V
IN
= VDD
I
OL
= 8 mA
I
OH
=
−8
mA
Unloaded outputs
23
2.4
18
2.0
50
100
0.4
Test Conditions
Min
Typ
Max
0.8
Unit
V
V
mA
mA
V
V
mA
W
10. CLKIN input has a threshold voltage of VDD/2
11. Parameter is guaranteed by design and characterization. Not 100% tested in production
Table 7. SWITCHING CHARACTERISTICS FOR ASM3P622S00B/E
Parameter
Input Frequency
Output Frequency
Duty Cycle = (t
2
/ t
1
) * 100 (Notes 12, 13)
Output Rise Time (Notes 12, 13)
Output Fall Time (Notes 12, 13)
Output−to−output skew (Notes 12, 13)
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 13)
Device−to−Device Skew (Note 13)
Cycle−to−Cycle Jitter
(Notes 12, 13)
PLL Lock Time (Note 13)
30 pF load
Measured at VDD/2
Measured between 0.8 V and 2.0 V
Measured between 2.0 V and 0.8 V
All outputs equally loaded with SSOFF
Measured at VDD/2 with SSOFF
Measured at VDD/2 on the CLKOUT
pins of the device
Loaded outputs
< 8 MHz
> 8 MHz
Stable power supply, valid clock
presented on CLKIN pin
Test Conditions
Min
4
4
40
50
Typ
Max
20
20
60
2.5
2.5
250
±350
700
±1.6
±200
1.0
Unit
MHz
MHz
%
nS
nS
pS
pS
pS
nS
pS
mS
12. All parameters specified with 30 pF loaded outputs.
13. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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