September 2005
rev 0.5
3.3V Zero Delay Buffer
Features
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2304B
Configurations Table”.
Input frequency range: 4MHz to 20MHz
Multiple low-skew outputs.
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of four outputs.
Less than 200pS Cycle-to-Cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8-pin 150 mil SOIC
Package.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available
.
ASM5P2304B
has an on-chip PLL, which locks to an input clock,
presented on the REF pin. The PLL feedback is required to
be driven to FBK pin, and can be obtained from one of the
outputs.
The
input-to-output
propagation
delay
is
guaranteed to be less than 250pS, and the output-to-output
skew is guaranteed to be less than 200pS.
The ASM5P2304B has two banks of two outputs each.
Multiple ASM5P2304B devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
The
ASM5P2304B
is
available
in
two
different
configurations (Refer “ASM5P2304B Configurations Table).
The ASM5P2304B-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304B-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster. The ASM5P2304B-2 allows the user to
obtain REF and 1/2X or 2X frequencies on each output
bank. The exact configuration and output frequencies
depend on which output drives the feedback pin.
high-speed
clocks
in
PC,
Functional Description
ASM5P2304B is a versatile, 3.3V zero-delay buffer
designed
to
distribute
workstation, datacom, telecom and other high-performance
applications. It is available in an 8 pin package. The part
Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
September 2005
rev 0.5
ASM5P2304B Configurations
ASM5P2304B
Device
ASM5P2304B-1
ASM5P2304B-1H
ASM5P2304B-2
ASM5P2304B-2
ASM5P2304B-2H
ASM5P2304B-2H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
Reference
2 X Reference
Bank B Frequency
Reference
Reference
Reference /2
Reference
Reference /2
Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
1000
REF-Input to CLKA/CLKB Delay (pS)
500
0
-30
-500
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P2304B, the FBK
pin can be driven from any of the four available output pins.
The output driving the FBK pin will be driving a total load of
7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph. For applications requiring zero input-
output delay, all outputs including the one providing
feedback should be equally loaded. If input-output delay
adjustments are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be sure to
load outputs equally.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 13
September 2005
rev 0.5
Pin Configuration
REF
CLKA1
CLKA2
GND
1
2
3
4
8
7
6
5
FBK
V
DD
CLKB2
CLKB1
ASM5P2304B
ASM5P2304B
Pin Description for ASM5P2304B
Pin #
1
2
3
4
5
6
7
8
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
Pin Name
REF
1
CLKA1
2
CLKA2
2
GND
CLKB1
2
CLKB2
2
V
DD
FBK
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
PLL feedback input
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 13
September 2005
rev 0.5
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
reliability.
ASM5P2304B
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
Operating Conditions for ASM5P2304B Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, from 4MHz to 20MHz
Input Capacitance
3
Description
Min
3.0
0
Max
3.6
70
30
7
Unit
V
°C
pF
pF
Electrical Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
4
Output HIGH Voltage
4
V
IN
= 0V
V
IN
= V
DD
Test Conditions
Min
Max
0.8
Unit
V
V
2.0
50.0
100.0
0.4
2.4
µA
µA
V
V
I
OL
= 8mA (-1, -2)
I
OH
= 12mA (-1H, -2H)
I
OL
= -8mA (-1, -2)
I
OH
= -12mA (-1H, -2H)
Unloaded outputs, 20MHz REF (-1,-1H, -2,-2H)
I
DD
Supply Current
10
mA
Note:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 13
September 2005
rev 0.5
Switching Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
1/t
1
ASM5P2304B
Description
Output Frequency
5
Duty Cycle = (t
2
/ t
1
) * 100
(-1, -2, -1H, -2H)
5
Duty Cycle = (t
2
/ t
1
) * 100
(-1, -2,-1H, -2H)
5
Output Rise Time
(-1, -2)
5
Output Rise Time
(-1, -2)
5
Output Rise Time
(-1H, -2H)
5
Output Fall Time
(-1, -2)
5
Output Fall Time
(-1, -2)
5
Output Fall Time
(-1H, -2H)
Output-to-output skew on same bank
(-1, -2)
Output-to-output skew (-1H, -2H)
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A to output bank b skew
(-2)
Delay, REF Rising Edge to FBK Rising
5
Edge
Device-to-Device Skew
5
Output Slew Rate
5
Test Conditions
30pF load, -1,-1H,-2, -2H devices
Measured at 1.4V, F
OUT
= 20MHz
30pF load
Measured at 1.4V, F
OUT
= <20MHz
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 0.8V and 2.0V
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 2.0V and 0.8V
30pF load
Measured between 2.0V and 0.8V
15pF load
Measured between 2.0V and 0.8V
30pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
the device
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Stable power supply, valid clock
presented on REF and FBK pins
Min Typ Max Unit
4
40.0
45.0
50.0
50.0
20
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
0
0
1
175
200
100
400
pS
375
1.0
mS
pS
±250
500
pS
pS
V/nS
pS
MHz
%
%
nS
nS
nS
nS
nS
nS
t
3
t
3
t
3
t
4
t
4
t
4
t
5
t
6
t
7
t
8
t
J
Cycle-to-cycle jitter
5
(-1, -1H, -2H)
t
J
Cycle-to-cycle jitter
5
(-2)
PLL Lock Time
5
t
LOCK
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production
.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 13
