ASM690A/692A,
ASM802L/802M, ASM805L
mP
Power Supply Supervisor
with Battery Backup Switch
Description
The ASM690A / ASM692A / ASM802L / ASM802M / ASM805L
offers complete single chip solutions for power supply monitoring and
control battery functions in microprocessor systems. Each device
implements four functions: Reset control, watchdog monitoring,
battery−backup switching and power failure monitoring. In addition to
microprocessor reset under power−up and power−down conditions,
these devices provide battery−backup switching to maintain control in
power loss and brown−out situations. Additional monitoring
capabilities can provide an early warning of unregulated power supply
loss before the voltage regulator drops out. The important features of
these four functions are:
•
1.6 second watchdog timer to keep microprocessor responsive
•
4.40 V or 4.65 V VCC threshold for microprocessor reset at
power−up and power−down
•
SPDT (Single−pole, Double−throw) PMOS switch connects backup
power to RAM if VCC fails
•
1.25 V threshold detector for power loss or general purpose voltage
monitoring
These features are pin−compatible with the industry standard
power−supply supervisors. Short−circuit and thermal protection have
also been added. The ASM690A / ASM802L / ASM805L generate a
reset pulse when the supply voltage drops below 4.65 V and the
ASM692A / ASM802M generate a reset below 4.40 V. The ASM802L
/ ASM802M have power−fail accuracy to
±2%.
The ASM805L is the
same as the ASM690A except that RESET is provided instead of
RESET.
Features
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PDIP−8
P SUFFIX
CASE 646AA
SOIC−8
S SUFFIX
CASE 751BD
PIN CONFIGURATIONS
V
OUT
V
CC
GND
PFI
1
1
ASM690A,
ASM692A,
ASM802L,
ASM802M
V
BATT
RESET
WDI
PFO
V
OUT
V
CC
GND
PFI
V
BATT
ASM805L
RESET
WDI
PFO
(Top Views)
•
Two Precision Supply−voltage Monitor Options
•
•
•
•
•
•
•
•
•
•
•
4.65 V (ASM690A / ASM802L / ASM805L)
4.40 V (ASM692A / ASM802M)
Battery−backup Power Switch On−chip
Watchdog Timer: 1.6 Second Timeout
Power Failure / Low Battery Detection
Short Circuit Protection and Thermal Limiting
Small 8−pin SO and 8−pin PDIP Packages
No External Components
Specified Over Full Temperature Range
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Applications
Embedded Control Systems
Portable/Battery Operated Systems
Intelligent Instruments
Wireless Instruments
1
•
•
•
•
Wireless Communication Systems
PDAs and Hand−held Equipments
mP
/
mC
Power Supply Monitoring
Safety System
Publication Order Number:
ASM690A/D
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 3
ASM690A/692A, ASM802L/802M, ASM805L
Figure 1. Typical Operating Circuit
Figure 2. Block Diagram
Table 1. PIN DESCRIPTION
Pin Number
ASM690A/ASM692A
ASM802L/ASM802M
1
ASM805L
1
Name
V
OUT
Function
Voltage supply for RAM. When V
CC
is above the reset threshold, V
OUT
connects
to V
CC
through a P−Channel MOS device. If V
CC
falls below the reset threshold,
this output will be connected to the backup supply at V
BATT
(or V
CC
, whichever is
higher) through the MOS switch to provide continuous power to the CMOS RAM.
+5 V power supply input.
Ground.
Power failure monitor input. PFI is connected to the internal power fail comparat-
or which is referenced to 1.25 V. The power fail output (PFO) is active LOW but
remains HIGH if PFI is above 1.25 V. If this feature is unused, the PFI pin should
be connected to GND or V
OUT
.
Power−fail output. PFO is active LOW whenever the PFI pin is less than 1.25 V.
Watchdog input. The WDI input monitors microprocessor activity. An internal
timer is reset with each transition of the WDI input. If the WDI is held HIGH or
LOW for longer than the watchdog timeout period, typically 1.6 seconds, RESET
(or RESET) is asserted for the reset pulse width time, t
RS
, of 140 ms, minimum.
Active−LOW reset output. When triggered by V
CC
falling below the reset
threshold or by watchdog timer timeout, RESET pulses low for the reset pulse
width t
RS
, typically 200 ms. It will remain low if V
CC
is below the reset threshold
(4.65 V in ASM690A / ASM802L and 4.4 V in the ASM692A / ASM802L) and
remains low for 200 ms after V
CC
rises above the reset threshold.
Active−HIGH reset output. The inverse of RESET.
Auxiliary power or backup−battery input. V
BATT
should be connected to GND if
the function is not used. The input has about 40 mV of hysteresis to prevent rapid
toggling between V
CC
and V
BATT
.
2
3
4
2
3
4
V
CC
GND
PFI
5
6
5
6
PFO
WDI
7
−
RESET
−
8
7
8
RESET
V
BATT
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2
ASM690A/692A, ASM802L/802M, ASM805L
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Pin Terminal Voltage with Respect to Ground
V
CC
V
BATT
All other inputs (Note 1)
Input Current at V
CC
Input Current at V
BATT
Input Current at GND
Output Current
V
OUT
All other inputs
Rate of Rise: V
BATT
and V
CC
Continuous Power Dissipation
Plastic DIP (derate 9 mW/°C above 70°C)
SO (derate 5.9 mW/°C above 70°C)
Operating Temperature Range (C Devices)
Operating Temperature Range (E Devices)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
ESD rating
HBM
MM
0
−40
−65
Min
−0.3
−0.3
−0.3
Max
6.0
6.0
V
CC
+ 0.3
200
50
20
Short circuit protected
20
100
800
500
70
85
160
300
1
100
mA
V/ms
mW
Unit
V
mA
mA
mA
°C
°C
°C
°C
KV
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The input voltage limits on PFI and WDI may be exceeded if the current is limited to less than 10 mA.
Table 3. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 4.75 V to 5.5 V for the ASM690A / ASM802L /
ASM805L and V
CC
= 4.5 V to 5.5 V for the ASM692A / ASM802M; V
BATT
= 2.8 V; and T
A
= T
MIN
to T
MAX
.)
Parameter
V
CC
, V
BATT
Voltage
Range (Note 2)
Supply Current
Excluding I
OUT
I
SUPPLY
in Battery
Backup Mode
(Excluding I
OUT
)
V
BATT
Standby
Current (Note 3)
V
OUT
Output
I
S
V
CC
= 0 V, V
BATT
= 2.8 V
T
A
= 25°C
T
A
= T
MIN
to T
MAX
5.5 V > V
CC
> V
BATT
+ 0.2 V
I
OUT
= 5 mA
I
OUT
= 50 mA
V
OUT
in Battery
Backup Mode
I
OUT
= 250
mA,
V
CC
< V
BATT
−
0.2 V
T
A
= 25°C
T
A
= T
MIN
to T
MAX
−0.1
−1.0
V
CC
−0.025
V
CC
−0.25
V
BATT
−
0.1
V
CC
−
0.010
V
CC
−
0.10
V
BATT
−
0.001
V
Symbol
Conditions
Min
1.1
35
1.5
5.0
0.02
0.02
mA
V
Typ
Max
5.5
100
Unit
V
mA
mA
2. If V
CC
or V
BATT
is 0 V, the other must be greater than 2.0 V.
3. Battery charging−current is “−”. Battery discharge current is “+”.
4. WDI is guaranteed to be in an intermediate level state if WDI is floating and V
CC
is within the operating voltage range.
NOTE:
WDI input impedance is 50 kW. WDI is biased to 0.3 V
CC
.
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3
ASM690A/692A, ASM802L/802M, ASM805L
Table 3. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 4.75 V to 5.5 V for the ASM690A / ASM802L /
ASM805L and V
CC
= 4.5 V to 5.5 V for the ASM692A / ASM802M; V
BATT
= 2.8 V; and T
A
= T
MIN
to T
MAX
.) (continued)
Parameter
Battery Switch
Threshold,
V
CC
to V
BATT
Battery Switch over
Hysteresis
Reset Threshold
V
RT
ASM690A/802L/805L
ASM692A, ASM802M
ASM802L, T
A
= 25°C, V
CC
falling
ASM802M, T
A
= 25°C, V
CC
falling
Reset Threshold
Hysteresis
Reset Pulse Width
Reset Output
Voltage
t
RS
I
SOURCE
= 800
mA
I
SINK
= 3.2 mA
ASM69_AC, ASM802_C, V
CC
= 1.0 V, I
SINK
= 50
mA
ASM69_AE, ASM802_E, V
CC
= 1.2 V, I
SINK
= 100
mA
ASM805LC, I
SOURCE
= 4
mA,
V
CC
= 1.1 V
ASM805LE, I
SOURCE
= 4
mA,
V
CC
= 1.2 V
ASM805L, I
SOURCE
= 800
mA
ASM805L, I
SINK
= 3.2 mA
Watchdog Timeout
WDI Pulse Width
WDI Input Current
t
WD
t
WP
V
IL
= 0.4 V, V
IH
= 0.8 V
CC
WDI = V
CC
WDI = 0 V
WDI Input Threshold
(Note 4)
PFI Input Threshold
V
CC
= 5 V, Logic LOW
V
CC
= 5 V, Logic HIGH
ASM69_A, ASM805L, V
CC
= 5 V
ASM802_C/E, V
CC
= 5 V
PFI Input Current
PFO Output Voltage
I
SOURCE
= 800
mA
I
SINK
= 3.2 mA
2. If V
CC
or V
BATT
is 0 V, the other must be greater than 2.0 V.
3. Battery charging−current is “−”. Battery discharge current is “+”.
4. WDI is guaranteed to be in an intermediate level state if WDI is floating and V
CC
is within the operating voltage range.
NOTE:
WDI input impedance is 50 kW. WDI is biased to 0.3 V
CC
.
3.5
1.20
1.225
−25
V
CC
−
1.5
0.4
1.25
1.250
0.01
1.30
1.275
25
nA
V
V
−150
1.00
50
50
−50
0.8
V
150
1.60
0.8
0.9
V
CC
−
1.5
0.4
2.25
sec
ns
mA
140
V
CC
−
1.5
0.4
0.3
0.3
4.50
4.25
4.55
4.30
40
200
280
Symbol
V
CC
< V
RT
Conditions
Power Up
Power Down
Min
Typ
20
−20
40
4.65
4.40
4.75
4.50
4.70
4.45
mV
ms
V
Max
Unit
mV
mV
V
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4
ASM690A/692A, ASM802L/802M, ASM805L
Detailed Description
It is important to initialize a microprocessor to a known
state in response to specific events that could create code
execution errors and “lock−up”. The reset output of these
supervisory circuits send a reset pulse to the microprocessor
in response to power−up, power−down/power−loss or a
watchdog time−out.
RESET/RESET Timing
Application Information
Microprocessor Interface
Power−up reset occurs when a rising V
CC
reaches the
reset threshold, V
RT
, forcing a reset condition in which the
reset output is asserted in the appropriate logic state for the
duration of t
RS
. The reset pulse width, t
RS
, is typically
around 200 ms and is LOW for the ASM690A, ASM692A,
ASM802 and HIGH for the ASM805L.
Figure 3
shows the
reset pin timing.
Power−loss or “brown−out” reset occurs when V
CC
dips
below the reset threshold resulting in a reset assertion for the
duration of t
RS
. The reset signal remains asserted as long as
V
CC
is between V
RT
and 1.1 V, the lowest V
CC
for which
these devices can provide a guaranteed logic−low output. To
ensure logic inputs connected to the ASM690A /
ASM692A/ASM802 RESET pin are in a known state when
V
CC
is under 1.1 V, a 100 kW pull−down resistor at RESET
is needed: the logic−high ASM805L will need a pull−up
resistor to V
CC
.
Watchdog Timer
The ASM690 has logic−LOW RESET output while the
ASM805 has an inverted logic−HIGH RESET output.
Microprocessors with bidirectional reset pins can pose a
problem when the supervisory circuit and the
microprocessor output pins attempt to go to opposite logic
states. The problem can be resolved by placing a 4.7 kW
resistor between the RESET output and the microprocessor
reset pin. This is shown in
Figure 4.
Since the series resistor
limits drive capabilities, the reset signal to other devices
should be buffered.
A Watchdog time−out reset occurs when a logic “1” or
logic “0” is continuously applied to the WDI pin for more
than 1.6 seconds. After the duration of the reset interval, the
watchdog timer starts a new 1.6 second timing interval; the
microprocessor must service the watchdog input by
changing states or by floating the WDI pin before this
interval is finished. If the WDI pin is held either HIGH or
LOW, a reset pulse will be triggered every 1.8 seconds (the
1.6 second timing interval plus the reset pulse width t
RS
).
Figure 3. RESET/RESET Timing
Figure 4. Interfacing with Bi−directional
Microprocessor Reset Inputs
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