Features
•
Low-voltage and Standard-voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
– 2.5 (V
CC
= 2.5V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes are Allowed
Self-timed Write Cycle (10 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-lead JEDEC SOIC, 8-pin PDIP and 8-lead TSSOP Packages
•
•
•
•
•
•
•
•
•
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•
•
2-wire
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-pin PDIP,
(AT24C01A/02/04/08/16), 8-lead TSSOP (AT24C01A/02/04/08/16) and 8-lead
JEDEC SOIC (AT24C01A/02/04/08/16) packages and is accessed via a 2-wire serial
interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to
5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
NC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
AT24C01A
AT24C02
AT24C04
AT24C08
AT24C16
8-pin PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0180F–06/01
1
Absolute Maximum Ratings
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Block Diagram
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bi-directional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or
open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1
and A0 pins are device address inputs that are hard wired
for the AT24C01A and the AT24C02. As many as eight
1K/2K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device
Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire
addressing and a total of four 4K devices may be
2
addressed on a single bus system. The A0 pin is a
no connect.
The AT24C08 only uses the A2 input for hardwire address-
ing and a total of two 8K devices may be addressed on a
single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the device address pins, which
limits the number of devices on a single bus to one. The
A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP):
The AT24C01A/02/04/16 has a
Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect
pin is connected to V
CC
, the write protection feature is
enabled and operates as shown in the following table.
AT24C01A/02/04/08/16
AT24C01A/02/04/08/16
Part of the Array Protected
24C01A
Full (1K)
Array
24C02
Full (2K)
Array
24C04
Full (4K)
Array
24C08
Normal
Read/
Write
Operation
24C16
Upper
Half
(8K)
Array
WP Pin
Status
At V
CC
At GND
Normal Read/Write Operations
Memory Organization
AT24C01A, 1K SERIAL EEPROM:
Internally organized
with 16 pages of 8 bytes each, the 1K requires a 7-bit data
word address for random word addressing.
AT24C02, 2K SERIAL EEPROM:
Internally organized with
32 pages of 8 bytes each, the 2K requires an 8-bit data
word address for random word addressing.
AT24C04, 4K SERIAL EEPROM:
Internally organized with
32 pages of 16 bytes each, the 4K requires a 9-bit data
word address for random word addressing.
AT24C08, 8K SERIAL EEPROM:
Internally organized with
64 pages of 16 bytes each, the 8K requires a 10-bit data
word address for random word addressing.
AT24C16, 16K SERIAL EEPROM:
Internally organized
with 128 pages of 16 bytes each, the 16K requires an 11-bit
data word address for random word addressing.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
°
C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
°
C to +85
°
C, V
CC
= +1.8V to +5.5V, T
AC
= 0
°
C to +70
°
C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 1.8V
Standby Current V
CC
= 2.5V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
I
OL
= 2.1 mA
READ at 100 kHz
WRITE at 100 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
x 0.7
Test Condition
Min
1.8
2.5
2.7
4.5
0.4
2.0
0.6
1.4
1.6
8.0
0.10
0.05
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
3.0
4.0
4.0
18.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
V
V
mA
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
Output Low Level V
CC
= 1.8V
I
OL
= 0.15 mA
1. V
IL
min and V
IH
max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from T
A
= -40
°
C to +85
°
C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
(1)
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Byte Mode
1M
4.7
100
10
1M
0.1
4.7
4.0
4.7
0
200
1.0
300
0.6
50
10
4.7
4.0
100
4.5
0.1
1.2
0.6
0.6
0
100
0.3
300
Min
Max
100
1.2
0.6
50
0.9
5.0-volt
Min
Max
400
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION:
A high-to-low transition of SDA with
SCL high is a start condition which must precede any
other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION:
A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE:
All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE:
The AT24C01A/02/04/08/16 features a
low-power standby mode which is enabled: (a) upon
power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
4
AT24C01A/02/04/08/16
AT24C01A/02/04/08/16
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
t
WR(1)
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
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