AT24C01D and AT24C02D
I
2
C-Compatible (2-wire) Serial EEPROM
1-Kbit (128 x 8) or 2-Kbit (256 x 8)
DATASHEET
Features
Low voltage operation
̶
1.7V (V
CC
= 1.7V to 3.6V)
Internally organized 128 x 8 (1K) or 256 x 8 (2K)
I
2
C-Compatible (2-wire) serial interface
Schmitt Triggers, filtered inputs for noise suppression
Bidirectional data transfer protocol
400kHz (1.7V) and 1MHz (2.5V) compatibility
Write Protect pin for full array hardware data protection
Ultra low active current (1mA max) and standby current (0.8μA max)
8-byte Page Write mode
̶
Partial page writes allowed
Random and Sequential Read modes
Self-timed write cycle within 5ms max
High reliability
̶
̶
Endurance: 1,000,000 write cycles
Data retention: 100 years
̶
8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP,
(1)
5-lead SOT23, and
8-ball VFBGA
Green package options (Lead-free/Halide-free/RoHS Compliant)
Die sale options: wafer form and tape and reel available
Description
The Atmel
®
AT24C01D/02D provides 1,024/2,048 bits of Serial Electrically
Erasable and Programmable Read-Only Memory (EEPROM) organized as
128/256 words of eight bits each. The device’s cascadable feature allows up to
eight devices to share a common 2-wire bus. These device are optimized for use
in many industrial and commercial applications where low-power and low-voltage
operation are essential. Both devices are available in space-saving 8-lead SOIC,
8-lead TSSOP, 8-pad UDFN, 8-lead PDIP,
(1)
5-lead SOT23, and
8-ball VFBGA packages. The entire family of packages operates from 1.7V to
3.6V.
Note:
1.
Contact Atmel Sales for availability of this package.
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
1.
Pin Descriptions and Pinouts
Table 1-1.
Pin
Number
Pin Descriptions
Pin
Symbol
Asserted
State
Pin
Type
Pin Name and Functional Description
Device Address Inputs:
The A
0
, A
1
, and A
2
pins are used to select the
hardware device address and correspond to the seventh, sixth, and fifth bit
of the I
2
C seven bit slave address. These pins can be directly connected to
V
CC
or GND, allowing up to eight devices on the same bus.
Refer to
Note 1
for behavior of the pin when not connected.
Ground:
The ground reference for the power supply. GND should be
connected to the system ground.
Serial Data:
The SDA pin is an open-drain bidirectional input/output pin
used to serially transfer data to and from the device.
1, 2, 3
A
0
, A
1
, A
2
—
Input
4
GND
—
Power
5
SDA
The SDA pin must be pulled-high using an external pull-up resistor (not to
exceed 10K in value) and may be wire-ORed with any number of other
open-drain or open-collector pins from other devices on the same bus.
Serial Clock:
The SCL pin is used to provide a clock to the device and to
control the flow of data to and from the device. Command and input data
present on the SDA pin is always latched in on the rising edge of SCL,
while output data on the SDA pin is clocked out on the falling edge of SCL.
The SCL pin must either be forced high when the serial bus is idle or
pulled-high using an external pull-up resistor.
—
Input/
Output
6
SCL
—
Input
7
WP
Write Protect:
Connecting the WP pin to GND will ensure normal write
operations.When the WP pin is connected to VCC, all write operations to
the memory are inhibited.
Refer to
Note 1
for behavior of the pin when not connected.
Device Power Supply:
The V
CC
pin is used to supply the source voltage to
the device. Operations at invalid V
CC
voltages may produce spurious
results and should not be attempted.
High
Input
8
V
CC
1.
—
Power
Note:
If the A
0
, A
1
, A
2
, or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide
variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong.
Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x V
CC
), the pull-down mechanism
disengages. Atmel recommends connecting these pins to a known state whenever possible.
8-lead SOIC
A
0
A
1
A
2
GND
1
2
3
4
8
7
6
5
8-lead TSSOP
V
CC
WP
SCL
SDA
A
0
A
1
A
2
GND
1
2
3
4
8
7
6
5
8-pad UDFN
V
CC
WP
SCL
SDA
A
0
A
1
A
2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Top View
8-lead PDIP
A
0
A
1
A
2
GND
1
2
3
4
8
7
6
5
Top View
5-lead SOT23
V
CC
WP
SCL
SDA
SCL
GND
SDA
1
2
3
4
5
(1)
Top View
8-ball VFBGA
A
0
A
1
A
2
V
CC
GND
1
2
3
4
8
7
6
5
WP
V
CC
WP
SCL
SDA
Top View
Top View
Top View
Note: Package drawings are not to scale
Note:
1.
Refer to
“Device Addressing” on page 7
for details about addressing the SOT23 version of the device.
2
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
2.
Device Block Diagram
A
0
Hardware
Address
Comparator
High Voltage
Generation Circuit
Memory
System Control
Module
Power
On Reset
Generator
V
CC
EEPROM Array
Row Decoder
A
1
Write
Protection
Control
WP
1 page
Address Register
and Counter
Column Decoder
A
2
Data Register
Start
Stop
Detector
SCL
D
OUT
Data & ACK
Input/Output Control
D
IN
GND
SDA
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
3
3.
Device Operation and Communication
The AT24C01D/02D operates as a slave device and utilizes a simple I
2
C-compatible 2-wire digital serial interface
to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls all
Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can
transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is
used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command and
data information from the Master as well as to send data back to the Master. Data is always latched into the
AT24C01D/02D on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the
SCL and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of
input spikes and bus noise.
All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been
transferred, the receiving device must respond with either an acknowledge (ACK) or a no-acknowledge (NACK)
response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master; Therefore, nine clock
cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or
Write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer
and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable
while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will
occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master and
the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is
determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the
logic-high state at the same time.
3.1
Clock and Data Transition Requirements
The SDA pin is an open drain terminal and therefore must be pulled high with an external pull-up resistor. Data on
the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a
Start or Stop condition as defined below.
3.2
3.2.1
Start and Stop Conditions
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable
Logic 1 state and will bring the device out of standby mode. The Master uses a Start condition to initiate any data
transfer sequence; therefore, every command must begin with a Start condition. The device will continuously
monitor the SDA and SCL pins for a Start condition but will not respond unless one is detected. See
Figure 3-1
for
more details.
3.2.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the
Logic 1 state. The Master can use the Stop condition to end a data transfer sequence with the AT24C01D/02D
which will subsequently return to standby mode. The Master can also utilize a repeated Start condition instead of a
Stop condition to end the current data transfer if the Master will perform another operation. See
Figure 3-1
for more
details.
4
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
3.3
Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the Master that it has successfully
received the data byte by responding with what is known as an acknowledge (ACK). An ACK is accomplished by
the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle followed by the
receiving device responding with a Logic 0 during the entire high period of the ninth clock cycle.
When the AT24C01D/02D is transmitting data to the Master, the Master can indicate that it is done receiving data
and wants to end the operation by sending a Logic 1 response to the AT24C01D/02D instead of an ACK response
during the ninth clock cycle. This is known as a no-acknowledge (NACK) and is accomplished by the Master
sending a Logic 1 during the ninth clock cycle, at which point the AT24C01D/02D will release the SDA line so the
Master can then generate a Stop condition.
The transmitting device, which can be the bus Master or the Serial EEPROM, must release the SDA line at the
falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a Logic 0 to ACK the
previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the
transmitter to continue sending new data. A timing diagram has been provided in
Figure 3-1
to better illustrate
these requirements.
Figure 3-1.
Start Condition, Data Transitions, Stop Condition and Acknowledge
SDA
Must Be
Stable
SDA
Must Be
Stable
Acknowledge Window
SCL
1
2
8
9
Stop
Condition
SDA
Start
Condition
SDA
Change
Allowed
SDA
Change
Allowed
Acknowledge
Valid
The transmitting device (Master or Slave)
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
The receiver (Master or Slave)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
3.4
Standby Mode
The AT24C01D/02D features a low power standby mode which is enabled when any one of the following occurs:
A valid power-up sequence is performed (see
Section 8.6, “Power-Up Requirements and Reset Behavior”).
A Stop condition is received by the device unless it initiates an internal write cycle (see
Section 5.).
At the completion of an internal write cycle (see
Section 5., “Write Operations”).
An unsuccessful match of the device type identifier or hardware address in the Device Address byte occurs
(see
Section 4.1, “Device Addressing”).
The bus Master does not ACK the receipt of data read out from the device; instead it sends a NACK
response (see
Section 6., “Read Operations”).
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
5
微控制器 MCU
