Features
•
Single 2.7V - 3.6V Supply
•
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS
™
Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (t
V
) of 5ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 16 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
Fast Program and Erase Times
– 1.0ms Typical Page Program (256 Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5mA Active Read Current (Typical at 20MHz)
– 5μA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
•
•
8-Mbit
2.7V Minimum
SPI Serial Flash
Memory
AT25DF081A
•
•
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8715C–SFLSH–1/2013
1.
Description
The Adesto
®
AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high-vol-
ume consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the AT25DF081A, with its erase granularity as small
as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM
devices.
The physical sectoring and the erase block sizes of the AT25DF081A have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same
overall device density.
The AT25DF081A also offers a sophisticated method for protecting individual sectors against erroneous or mali-
cious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system
can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array
securely protected. This is useful in applications where program code is patched or updated on a subroutine or
module basis, or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF081A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors
do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DF081A incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be per-
manently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time Pro-
grammable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DF081A supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2
AT25DF081A
8715C–SFLSH–1/2013
AT25DF081A
2.
Pin Descriptions and Pinouts
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT):
The SI pin is used to shift data into the device.
The SI pin is used for all data input including command and address sequences. Data on the
SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow
two bits of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To
maintain consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout
the document with exception to sections dealing with the Dual-Output Read Array command
in which it will be referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT):
The SO pin is used to shift data out from the
device. Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI)
to allow two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of
SCK. To maintain consistency with SPI nomenclature, the SOI pin will be referenced as SO
throughout the document with exception to sections dealing with the Dual-Input Byte/Page
Program command in which it will be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. Please
refer to
“Protection Commands and Features” on page 17
for more details on protection
features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 41
for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever possible.
Asserted
State
Type
Table 2-1.
Symbol
CS
Low
Input
SCK
-
Input
SI (SIO)
-
Input/Output
SO (SOI)
-
Output/Input
WP
Low
Input
HOLD
Low
Input
3
8715C–SFLSH–1/2013
Table 2-1.
Symbol
V
CC
Pin Descriptions (Continued)
Name and Function
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the
system ground.
Asserted
State
-
Type
Power
GND
-
Power
Figure 2-1.
8-SOIC (Top View)
CS
SO (SOI)
WP
GND
1
2
3
4
8
7
6
5
Figure 2-2.
VCC
HOLD
SCK
SI (SIO)
8-UDFN (Top View)
CS
SO (SOI)
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI (SIO)
3.
Block Diagram
Figure 3-1.
Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SCK
SI (SIO)
SO (SOI)
INTERFACE
CONTROL
AND
LOGIC
SRAM
DATA BUFFER
Y-DECODER
Y-GATING
ADDRESS LATCH
WP
HOLD
X-DECODER
FLASH
MEMORY
ARRAY
4
AT25DF081A
8715C–SFLSH–1/2013
AT25DF081A
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DF081A can be erased in four levels of granularity
including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which
each sector can be individually protected from program and erase operations. The size of the physical sectors is
optimized for both code and data storage applications, allowing both code and data segments to reside in their own
isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
Figure 4-1.
Memory Architecture Diagram
Block Erase Detail
Internal Sectoring for
Sector Protection
Function
64KB
32KB
Block Erase
Block Erase
(D8h Command) (52h Command)
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
•••
Block Address
Range
0FFFFFh
0FEFFFh
0FDFFFh
0FCFFFh
0FBFFFh
0FAFFFh
0F9FFFh
0F8FFFh
0F7FFFh
0F6FFFh
0F5FFFh
0F4FFFh
0F3FFFh
0F2FFFh
0F1FFFh
0F0FFFh
0EFFFFh
0EEFFFh
0EDFFFh
0ECFFFh
0EBFFFh
0EAFFFh
0E9FFFh
0E8FFFh
0E7FFFh
0E6FFFh
0E5FFFh
0E4FFFh
0E3FFFh
0E2FFFh
0E1FFFh
0E0FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F7000h
0F6000h
0F5000h
0F4000h
0F3000h
0F2000h
0F1000h
0F0000h
0EF000h
0EE000h
0ED000h
0EC000h
0EB000h
0EA000h
0E9000h
0E8000h
0E7000h
0E6000h
0E5000h
0E4000h
0E3000h
0E2000h
0E1000h
0E0000h
Page Program Detail
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
•••
Page Address
Range
0FFFFFh
0FFEFFh
0FFDFFh
0FFCFFh
0FFBFFh
0FFAFFh
0FF9FFh
0FF8FFh
0FF7FFh
0FF6FFh
0FF5FFh
0FF4FFh
0FF3FFh
0FF2FFh
0FF1FFh
0FF0FFh
0FEFFFh
0FEEFFh
0FEDFFh
0FECFFh
0FEBFFh
0FEAFFh
0FE9FFh
0FE8FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FFF00h
0FFE00h
0FFD00h
0FFC00h
0FFB00h
0FFA00h
0FF900h
0FF800h
0FF700h
0FF600h
0FF500h
0FF400h
0FF300h
0FF200h
0FF100h
0FF000h
0FEF00h
0FEE00h
0FED00h
0FEC00h
0FEB00h
0FEA00h
0FE900h
0FE800h
32KB
64KB
(Sector 15)
64KB
32KB
32KB
64KB
(Sector 14)
64KB
32KB
32KB
64KB
(Sector 0)
64KB
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00FFFFh
00EFFFh
00DFFFh
00CFFFh
00BFFFh
00AFFFh
009FFFh
008FFFh
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00F000h
00E000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017FFh
0016FFh
0015FFh
0014FFh
0013FFh
0012FFh
0011FFh
0010FFh
000FFFh
000EFFh
000DFFh
000CFFh
000BFFh
000AFFh
0009FFh
0008FFh
0007FFh
0006FFh
0005FFh
0004FFh
0003FFh
0002FFh
0001FFh
0000FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
001700h
001600h
001500h
001400h
001300h
001200h
001100h
001000h
000F00h
000E00h
000D00h
000C00h
000B00h
000A00h
000900h
000800h
000700h
000600h
000500h
000400h
000300h
000200h
000100h
000000h
•••
•••
•••
5
8715C–SFLSH–1/2013
