Features
•
Single 2.7V
−
3.6V Supply
•
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports RapidS Operation
Supports Dual-Input Program and Dual-Output Read
•
Very High Operating Frequencies
100MHz for RapidS
75MHz for SPI
Clock-to-Output (t
V
) of 5ns Maximum
•
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
64-Mbit, 2.7V
Minimum Serial
Peripheral Interface
Serial Flash Memory
AT25DF641
•
Individual Sector Protection with Global Protect/Unprotect Feature
128 Sectors of 64-Kbytes Each
•
Hardware Controlled Locking of Protected Sectors via
WP
P
in
•
Sector Lockdown
Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
•
128-Byte Programmable OTP Security Register
•
Flexible Programming
Byte/Page Program (1- to 256-Bytes)
•
Fast Program and Erase Times
1.0ms Typical Page Program (256-Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
250ms Typical 32-Kbyte Block Erase Time
400ms Typical 64-Kbyte Block Erase Time
•
Program and Erase Suspend/Resume
•
Automatic Checking and Reporting of Erase/Program Failures
•
Software Controlled Reset
•
JEDEC Standard Manufacturer and Device ID Read Methodology
•
Low Power Dissipation
5mA Active Read Current (Typical at 20MHz)
5µA Deep Power-Down Current (Typical)
•
Endurance: 100,000 Program/Erase Cycles
•
Data Retention: 20 Years
•
Complies with Full Industrial Temperature Range
•
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
16-Lead SOIC (300-mil wide)
8-Contact Very Thin DFN (6 x 8mm)
3680F–DFLASH–4/10
Description
The AT25DF641 is a s erial interface Flash memory device designed for use in a w ide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external
RAM for execution. The flexible erase architecture of the AT25DF641, with its erase granularity as small as 4-
Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DF641 have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while still maintaining the
same overall device density.
The AT25DF641 also offers a sophisticated method for protecting individual sectors against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a
system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory
array securely protected. This is useful in applications where program code is patched or updated on a subroutine
or module basis or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF641 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since
sectors do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DF641 incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be
permanently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a s pecialized OTP (One-Time
Programmable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DF641 supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2
AT25DF641
3680F–DFLASH–4/10
AT25DF641
1.
Pin Descriptions and Pinouts
Table 1-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the
CS
pin selects the device. When the
CS
pin is
deasserted, the device will be deselected and normally be placed in standby
mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance
state. When the device is deselected, data will not be accepted on the SI pin.
A high-to-low transition on the
CS
pin is required to start an operation, and a low-
to-high transition is required to end an operation. When ending an internally self-
timed operation such as a program or erase cycle, the device will not enter the
standby mode until the completion of the operation.
Asserted
State
Type
CS
Low
Input
SCK
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to
control the flow of data to and from the device. Command, address, and input
data present on the SI pin is always latched in on the rising edge of SCK, while
output data on the SO pin is always clocked out on the falling edge of SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT):
The SI pin is used to shift data into
the device. The SI pin is used for all data input including command and address
sequences. Data on the SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin
(SIO) to allow two bits of data (on the SO and SIO pins) to be clocked out on
every falling edge of SCK. To maintain consistency with SPI nomenclature, the
SIO pin will be referenced as SI throughout the document with exception to
sections dealing with the Dual-Output Read Array command in which it will be
referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected
(
CS
is deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT):
The SO pin is used to shift data
out from the device. Data on the SO pin is always clocked out on the falling edge
of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input
pin (SOI) to allow two bits of data (on the SOI and SI pins) to be clocked in on
every rising edge of SCK. To maintain consistency with SPI nomenclature, the
SOI pin will be referenced as SO throughout the document with exception to
sections dealing with the Dual-Input Byte/Page Program command in which it will
be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected
( CS is deasserted).
WRITE PROTECT:
The WP pin controls the hardware locking feature of the
device. Please refer to “Protection Commands and Features” on page 21 for more
details on protection features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware
controlled protection will not be used. However, it is recommended that the WP
pin also be externally connected to V
CC
whenever possible.
−
Input
SI (SIO)
−
Input/Output
SO (SOI)
−
Output/Input
WP
Low
Input
3
3680F–DFLASH–4/10
Table 1-1.
Symbol
Pin Descriptions (Continued)
Name and Function
HOLD:
The HOLD pin is used to temporarily pause serial communication without
Asserted
State
Type
HOLD
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the
SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-
impedance state.
The
CS
pin must be asserted, and the SCK pin must be in the low state in order for a
Hold condition to start. A Hold condition pauses serial communication only and does not
have an effect on internally self-timed operations such as a program or erase cycle.
Please refer to “Hold” on page 45 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not
be used. However, it is recommended that the HOLD pin also be externally connected to
V
CC
whenever possible.
Low
Input
V
CC
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the
device.
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the
system ground.
−
Power
GND
−
Power
Figure 1-1.
CS
SO (SOI)
WP
GND
1
2
3
4
8-VDFN (Top View)
8
V
CC
7
HOLD
6
SCK
5
SI (SIO)
Figure 1-2.
HOLD
V
CC
NC
NC
NC
NC
CS
SO (SOI)
1
2
3
4
5
6
7
8
16-SOIC (Top View)
16
15
14
13
12
11
10
9
SCK
SI(SIO)
NC
NC
NC
NC
GND
WP
4
AT25DF641
3680F–DFLASH–4/10
AT25DF641
2.
Block Diagram
Figure 2-1.
Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
SCK
SI (SIO)
SO (SOI)
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
Y-DECODER
Y-GATING
WP
HOLD
X-DECODER
FLASH
MEMORY
ARRAY
5
3680F–DFLASH–4/10
