Features
•
Serial Peripheral Interface (SPI) Compatible
•
Supports SPI Modes 0 (0,0) and 3 (1,1)
•
•
•
– Datasheet describes Mode 0 Operation
50 MHz Clock Rate
Byte Mode and Page Mode Program (1 to 256 Bytes) Operations
Sector/Block/Page Architecture
– 256 byte Pages per Sector
– Eight 4 Kbyte Sectors per Block
– Four uniform 32 Kbyte Blocks
Self-timed Sector, Block and Chip Erase
Product Identification Mode with JEDEC Standard
Low-voltage Operation
– 2.7V (V
CC
= 2.7V to 3.6V)
Hardware and Software Write Protection
– Device protection with Write Protect (WP) Pin
– Write Enable and Write Disable Instructions
– Software Write Protection:
Upper 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array
Flexible Op Codes for Maximum Compatibility
Self-timed Program Cycle
– 30 µs/Byte Typical
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
– Endurance: 10,000 Write Cycles Typical
8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP)
•
•
•
•
High Speed
Small Sectored
SPI Flash
Memory
1M (131,072 x 8)
•
•
•
•
•
AT25FS010
Description
The AT25FS010 provides 1,048,576 bits of serial reprogrammable Flash memory
organized as 131,072 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25FS010 is available in a space-saving 8-lead JEDEC SOIC and
8-lead Ultra Thin SAP packages.
Table 1.
Pin Configuration
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial
Input
8-lead SAP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Advance
Information
8-lead JEDEC SOIC
___
VCC
_____
8
HOLD 7
SCK 6
SI 5
1 CS
2
___
SO
3 WP
4 GND
Bottom View
5167B–SFLSH–1/07
The AT25FS010 is enabled through the Chip Select pin (CS) and accessed via a 3-wire
interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for upper 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array
is enabled by programming the status register. Separate write enable and write disable
instructions are provided for additional data protection. Hardware data protection is pro-
vided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Absolute Maximum Ratings*
Operating Temperature....................................–40°C to +85°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +5.0V
Maximum Operating Voltage ............................................ 4.2V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1.
Block Diagram
524,288 x 8
2
AT25FS010
5167B–SFLSH–1/07
AT25FS010
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +3.6V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
Table 3.
DC Characteristics (Preliminary – Subject to Change)
Applicable over recommended operating range from: T
AI
=
–
40°C to +85°C, V
CC
= +2.7V to +3.6V,
T
AC
= 0°C to +70°C, V
CC
= +2.7V to +3.6V (unless otherwise noted)
Symbol
V
CC
I
CC1
I
CC2
I
SB
I
IL
I
OL
V
IL(1)
V
IH(1)
V
OL
V
OH
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.7V
≤
V
CC
≤
3.6V
I
OL
= 0.15 mA
I
OH
= -100 µA
V
CC
- 0.2
V
CC
= 3.6V at 20 MHz, SO = Open Read
V
CC
= 3.6V at 20 MHz, SO = Open Write
V
CC
= 2.7V, CS = V
CC
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
, T
AC
= 0°C to 70°C
-3.0
-3.0
-0.6
V
CC
x 0.7
Test Condition
Min
2.7
10.0
15.0
2.0
Typ
Max
3.6
17.0
45.0
10.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.2
Units
V
mA
mA
µA
µA
µA
V
V
V
V
1. V
IL
and V
IH
max are reference only and are not tested.
3
5167B–SFLSH–1/07
Table 4.
AC Characteristics (Preliminary – Subject to Change)
Applicable over recommended operating range from T
A
=
–
40°C to +85°C, V
CC
= +2.7V to +3.6V
C
L
= 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
f
SCK
t
RI
t
FI
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
SU
t
H
t
HD
t
CD
t
V
t
HO
t
LZ
t
HZ
t
DIS
t
se
t
be
t
ce
t
SR
t
BPC
Endurance
(2)
Notes:
Parameter
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Sector Erase Time
Block Erase Time
Chip Erase Time
Status Register Write Cycle Time
Byte Program Cycle Time
(1)
30
10K
50
200
1.6
0
9
9
9
200
500
4
60
50
9
9
100
5
5
5
5
5
5
9
Min
0
Typ
Max
50
5
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
s
ms
µs
Write Cycles
(3)
1. The programming time for n bytes will be equal to n x t
BPC
.
2. This parameter is characterized at 3.0V.
3. One write cycle consists of erasing a sector, followed by programming the same sector.
4
AT25FS010
5167B–SFLSH–1/07
AT25FS010
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the AT25FS010 always
operates as a slave.
TRANSMITTER/RECEIVER:
The AT25FS010 has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25FS010, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT:
The AT25FS010 is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the AT25FS010.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The AT25FS010 has a write lockout feature that can be activated by
asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is “1”, all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25FS010 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
Operating Features
Recommended Power-up
When the power supply is turned on, V
cc
rises monotonically from ground to the full
operating V
cc
. During this time, the Chip Select (CS) signal is not allowed to float and
must follow V
cc
. For this reason, it is recommended to use a suitable pull-up resistor
connected between CS and V
cc
. The device is ready for communication once a stable
V
cc
is reached within the specified operating voltage range.
The device must be deselected and in Standby and Write Disabled mode prior to V
cc
power down sequence. This means there should be no write operation/internal Write
cycle or read operation in progress during the Chip Select (CS) line must be allowed to
follow V
cc
during power down. After power down, it is recommended V
cc
should be held
at ground level for at least 0.5 seconds before power up again.
Recommended Power-
down
5
5167B–SFLSH–1/07
