Features
•
Single 2.7V to 3.6V Supply
•
Hardware and Software Data Protection
•
Low Power Dissipation
– 15mA Active Current
– 20µA CMOS Standby Current
Fast Read Access Time – 200ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Only
•
•
•
•
•
•
•
•
64K (8K x 8)
Battery-Voltage
Parallel
EEPROM
with Page Write
and Software
Data Protection
AT28BV64B
1. Description
The Atmel
®
AT28BV64B is a high-performance electrically erasable programmable
read only-memory (EEPROM). Its 64K of memory is organized as 8,192 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20µA.
The AT28BV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64 byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high quality and manufactur-
ability. A software data protection mechanism guards against inadvertent writes. The
device also includes an extra 64 bytes of EEPROM for device identification or
tracking.
Atmel-0299K-PEEPROM-AT28BV64B-Datasheet_072014
2. Pin Configurations
Pin Name
A0 - A12
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
2.2
32-lead PLCC Top View
A7
A12
NC
DC
VCC
WE
NC
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2.1
28-lead SOIC Top View
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2.3
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
28-lead TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
2
AT28BV64B
Atmel-0299K-PEEPROM-AT28BV64B-Datasheet_072014
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
AT28BV64B
3. Block Diagram
4. Device Operation
4.1
Read
The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100µs (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded, the AT28BV64B will cease accepting data and commence the internal pro-
gramming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page
write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
3
Atmel-0299K-PEEPROM-AT28BV64B-Datasheet_072014
4.4
DATA Polling
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the
write cycle.
4.5
Toggle Bit
In addition to DATA Polling, the AT28BV64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
(a) V
CC
power-on delay – once V
CC
has reached 1.8V (typical) the device will automatically time
out 10 ms (typical) before allowing a write; (b) write inhibit–holding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filter–pulses of less than 15ns (typical) on the WE
or CE inputs will not initiate a write cycle.
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV64B.
Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature.
A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write
operation. All software write commands must obey the page mode write timing specifications.
The data in the 3-byte command sequence is not written to the device; the addresses in the
command sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of t
WC
, read operations will effec-
tively be polling operations.
4.6.2
4.7
Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 0000H to 003FH, the additional bytes may
be written to or read from in the same manner as the regular memory array.
4
AT28BV64B
Atmel-0299K-PEEPROM-AT28BV64B-Datasheet_072014
AT28BV64B
5. DC and AC Operating Range
AT28BV64B-20
Operating Temperature (Case)
V
CC
Power Supply
-40C - 85C
2.7V to 3.6V
6. Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V ± 0.5V.
CE
V
IL
V
IL
V
IH
X
X
X
V
IL
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
V
H(3)
WE
V
IH
V
IL
X
V
IH
X
X
V
IL
High Z
High Z
I/O
D
OUT
D
IN
High Z
7. Absolute Maximum Ratings*
Temperature Under Bias ............................... -55C to +125C
Storage Temperature..................................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
5
Atmel-0299K-PEEPROM-AT28BV64B-Datasheet_072014
51单片机
