AT28HC64B
Features
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Fast Read Access Time - 55 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
Low Power Dissipation
40 mA Active Current
100
µA
CMOS Standby Current
Hardware and Software Data Protection
DATA Polling and Toggle Bit for End of Write Detection
High Reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 Years
Single 5V
±
10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28HC64B is a high-performance electrically erasable and programmable read
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 55 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100
µA.
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
(continued)
Pin Name
A0 - A12
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
64K (8K x 8)
High Speed
CMOS
E
2
PROM with
Page Write and
Software Data
Protection
Pin Configurations
TSOP
Top View
AT28HC64B
PDIP, SOIC
Top View
PLCC
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0274D
2-267
Description
(Continued)
writing of up to 64-bytes simultaneously. During a write cy-
cle, the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA Polling of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Atmel’s AT28HC64B has additional features to ensure
high quality and manufacturability. The device utilizes in-
ternal error correction for extended endurance and im-
proved data retention. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64-bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2-268
AT28HC64B
AT28HC64B
Device Operation
READ:
The AT28HC64B is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention in their systems.
BYTE WRITE:
A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started, it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a poll-
ing operation.
PAGE WRITE:
T h e p a g e w r i t e o p e r a t i o n o f t h e
AT28HC64B allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; after the first byte is written, it can then be fol-
lowed by 1 to 63 additional bytes. Each successive byte
must be loaded within 150
µs
(t
BLC
) of the previous byte.
If the t
BLC
limit is exceeded, the AT28HC64B will cease
accepting data and commence the internal programming
operation. All bytes during a page write operation must re-
side on the same page as defined by the state of the A6 to
A12 inputs. For each WE high to low transition during the
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page
are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec-
essary cycling of other bytes within the page does not oc-
cur.
DATA POLLING:
The AT28HC64B features DATA Poll-
ing to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written
will result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at any time during the
write cycle.
TOGGLE BIT:
I n a d d i t i o n t o DATA P o l l i n g , t he
AT28HC64B provides another method for determining the
end of a write cycle. During the write operation, succes-
sive attempts to read data from the device will result in
I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling, and valid data will be
read. Toggle bit reading may begin at any time during the
write cycle.
DATA PROTECTION:
If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent writes to the AT28HC64B in
the following ways: (a) V
CC
sense - if V
CC
is below 3.8V
(typical), the write function is inhibited; (b) V
CC
power-on
delay - once V
CC
has reached 3.8V, the device will auto-
matically time out 5 ms (typical) before allowing a write; (c)
write inhibit - holding any one of OE low, CE high or WE
high inhibits write cycles; (d) noise filter - pulses of less
than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
SOFTWARE DATA PROTECTION:
A software-control-
led data protection feature has been implemented on the
AT28HC64B. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC64B
is shipped from Atmel with SDP disabled.
SDP is enabled by the user issuing a series of three write
commands in which three specific bytes of data are written
to three specific addresses (refer to the
Software Data
Protection Algorithm
diagram in this data sheet). After writ-
ing the 3-byte command sequence and waiting t
WC
, the
entire AT28HC64B will be protected against inadvertent
writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the
AT28HC64B. This is done by preceding the data to be
written by the same 3-byte command sequence used to
enable SDP.
Once set, SDP remains active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP, and SDP protects the AT28HC64B during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. The data in the enable and disable command se-
quences is not actually written into the device; their ad-
dresses may still be written with user data in either a byte
or page write operation.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device, however.
For the duration of t
WC
, read operations will effectively be
polling operations.
(continued)
2-269
Device Operation
(Continued)
DEVICE IDENTIFICATION:
A n e x t r a 6 4 - b y t e s o f
EEPROM memory are available to the user for device
identification. By raising A9 to 12V
±
0.5V and using ad-
dress locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the
regular memory array.
DC and AC Operating Range
AT28HC64B-55
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
5V
±
10%
0°C - 70°C
AT28HC64B-70
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT28HC64B-90
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT28HC64B-120
0°C - 70°C
-40°C - 85°C
5V
±
10%
Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
CE
V
IL
V
IL
V
IH
X
X
X
V
IL
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
V
H (3)
3. V
H
= 12.0V
±
0.5V.
WE
V
IH
V
IL
X
V
IH
X
X
V
IL
I/O
D
OUT
D
IN
High Z
High Z
High Z
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to the
AC Write Waveforms
diagrams
in this data sheet.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH
Note:
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Condition
V
IN
= 0V to V
CC
+ 1V
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
+ 1V
CE = 2.0V to V
CC
+ 1V
f = 5 MHz; I
OUT
= 0 mA
Com., Ind.
Min
Max
10
10
100
(1)
2
(1)
40
0.8
Units
µA
µA
µA
mA
mA
V
V
V
V
2.0
I
OL
= 2.1 mA
I
OH
= -400
µA
2.4
.40
1. I
SB1
and I
SB2
for the 55 ns part is 40 mA maximum.
2-270
AT28HC64B
AT28HC64B
AC Read Characteristics
AT28HC64B-55 AT28HC64B-70 AT28HC64B-90 AT28HC64B-120
Symbol Parameter
t
ACC
t
CE (1)
t
OE (2)
t
DF (3, 4)
t
OH
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE to Output Float
Output Hold
0
0
0
Min
Max
Min
Max
Min
Max
Min
Max
Units
ns
ns
ns
ns
ns
55
55
30
30
0
0
0
70
70
35
35
0
0
0
90
90
40
40
0
0
0
120
120
50
50
AC Read Waveforms
(1, 2, 3, 4)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE, whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
t
R
, t
F
< 5ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
C
IN
C
OUT
Note:
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
4
8
1. This parameter is characterized and is not 100% tested.
2-271
DSP 与 ARM 处理器
