Features
•
Fast Read Access Time – 70 ns
•
Automatic Page Write Operation
•
– Internal Address and Data Latches for 64 Bytes
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum (Standard)
2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)
– 1 to 64-byte Page Write Operation
Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling and Toggle Bit for End of Write Detection
High Reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
Single 5 V
±10%
Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option Only
•
•
•
•
•
•
•
•
•
64K (8K x 8)
High-speed
Parallel
EEPROM with
Page Write and
Software Data
Protection
AT28HC64B
1. Description
The AT28HC64B is a high-performance electrically-erasable and programmable read-
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 55 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel’s AT28HC64B has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an
extra 64 bytes of EEPROM for device identification or tracking.
0274L–PEEPR–2/3/09
2. Pin Configurations
Pin Name
A0 - A12
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
2.2
32-lead PLCC Top View
A7
A12
NC
DC
VCC
WE
NC
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2.1
28-lead SOIC Top View
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2.3
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
28-lead TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
2
AT28HC64B
0274L–PEEPR–2/3/09
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
AT28HC64B
3. Block Diagram
VCC
GND
OE
WE
CE
Y DECODER
ADDRESS
INPUTS
X DECODER
IDENTIFICATION
DATA INPUTS/OUTPUTS
I/O0 - I/O7
OE, CE and WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
4. Device Operation
4.1
Read
The AT28HC64B is accessed like a Static RAM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high-impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus contention in their systems.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
WC
, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28HC64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 µs (t
BLC
) of the previous
byte. If the t
BLC
limit is exceeded, the AT28HC64B will cease accepting data and commence
the internal programming operation. All bytes during a page write operation must reside on the
same page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition
during the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
4.4
DATA Polling
The AT28HC64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time
during the write cycle.
3
0274L–PEEPR–2/3/09
4.5
Toggle Bit
In addition to DATA Polling, the AT28HC64B provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling, and valid data will be read. Toggle bit reading may begin at any time during the write
cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
®
has incorporated both hardware and software features that will protect
the memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28HC64B in the following ways:
(a) V
CC
sense – if V
CC
is below 3.8 V (typical), the write function is inhibited; (b) V
CC
power-on
delay – once V
CC
has reached 3.8 V, the device will automatically time out 5 ms (typical)
before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhib-
its write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a write cycle.
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28HC64B.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28HC64B is shipped from Atmel with
SDP disabled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (refer to the “Software Data Protection
Algorithm” diagram on
page 10).
After writing the 3-byte command sequence and waiting t
WC
,
the entire AT28HC64B will be protected against inadvertent writes. It should be noted that
even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64B.
This is done by preceding the data to be written by the same 3-byte command sequence used
to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28HC64B during power-up and power-
down conditions. All command sequences must conform to the page write timing specifica-
tions. The data in the enable and disable command sequences is not actually written into the
device; their addresses may still be written with user data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device, however. For the dura-
tion of t
WC
, read operations will effectively be polling operations.
4.6.2
4.7
Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12 V
±0.5
V and using address locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the regular memory array.
4
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
5. DC and AC Operating Range
AT28HC64B-70
Operating Temperature (Case)
V
CC
Power Supply
-40°C - 85°C
5 V
±10%
AT28HC64B-90
-40°C - 85°C
5 V
±10%
AT28HC64B-120
-40°C - 85°C
5 V
±10%
6. Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
Notes:
1. X can be VIL or VIH.
2.
See “AC Write Waveforms” on page 8.
3. VH = 12.0 V ±0.5 V.
CE
V
IL
V
IL
V
IH
X
X
X
V
IL
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
V
H(3)
WE
V
IH
V
IL
X
V
IH
X
X
V
IL
High Z
High Z
I/O
D
OUT
D
IN
High Z
7. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .................................-0.6 V to +6.25 V
All Output Voltages
with Respect to Ground ...........................-0.6 V to V
CC
+ 0.6 V
Voltage on OE and A9
with Respect to Ground ..................................-0.6 V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
8. DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH
Note:
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1 mA
I
OH
= -400 µA
2.4
2.0
0.40
Condition
V
IN
= 0 V to V
CC
+ 1 V
V
I/O
= 0 V to V
CC
CE = V
CC
- 0.3 V to V
CC
+ 1 V
CE = 2.0 V to V
CC
+ 1 V
f = 5 MHz; I
OUT
= 0 mA
Min
Max
10
10
100
(1)
2
(1)
40
0.8
Units
µA
µA
µA
mA
mA
V
V
V
V
1. I
SB1
and I
SB2
for the 55 ns part is 40 mA maximum.
5
0274L–PEEPR–2/3/09
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