Features
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Single Supply Voltage, Range 2.7V to 3.6V
Single Supply for Read and Write
Software Protected Programming
Fast Read Access Time – 120 ns
Low Power Dissipation
– 15 mA Active Current
– 50 µA CMOS Standby Current
Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes
Two 8K Bytes Boot Blocks with Lockout
Fast Sector Program Cycle Time – 20 ms Max
Internal Program Control and Timer
DATA Polling for End of Program Detection
Typical Endurance > 10,000 Cycles
CMOS and TTL Compatible Inputs and Outputs
Green (Pb/Halide-free) Packaging Option
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1-Megabit
(128K x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT29BV010A
Not Recommended
for New Design
Contact
Atmel to discuss
the latest design in trends
and options
1. Description
The AT29BV010A is a 2.7-volt only in-system Flash Programmable and Erasable
Read Only Memory (Flash). Its 1 megabit of memory is organized as 131,072 words
by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technol-
ogy, the device offers access times to 120 ns, and a low 54 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 50µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
Low Voltage Flash family of products.
To allow for simple in-system reprogrammability, the AT29BV010A does not require
high input voltages for programming. The device can be operated with a single 2.7V to
3.6V supply. Reading data out of the device is similar to reading from an EPROM.
Reprogramming the AT29BV010A is performed on a sector basis; 128 bytes of data
are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are captured at
microprocessor speed and internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automati-
cally erase the sector and then program the latched data using an internal control
timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the
end of a program cycle has been detected, a new access for a read or program can
begin.
0519F–FLASH–9/08
2. Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
2.1
32-lead PLCC Top View
2.2
32-lead TSOP (Type 1) Top View
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
14
15
16
17
18
19
20
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
A12
A15
A16
NC
VCC
WE
NC
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2
AT29BV010A
0519F–FLASH–9/08
AT29BV010A
3. Block Diagram
4. Device Operation
4.1
Read
The AT29BV010A is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-
trol gives designers flexibility in preventing bus contention.
4.2
Software Data Protection Programming
The AT29BV010A has 1024 individual sectors, each 128 bytes. Using the software data protec-
tion feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The
AT29BV010A can only be programmed or reprogrammed using the software data protection
feature. The device is programmed on a sector basis. If a byte of data within the sector is to be
changed, data for the entire 128-byte sector must be loaded into the device. The data in any
byte that is not loaded during the programming of its sector will be indeterminate. The
AT29BV010A automatically does a sector erase prior to loading the data into the sector. An
erase command is not required.
Software data protection protects the device from inadvertent programming. A series of three
program commands to specific addresses with specific data must be presented to the device
before programming may occur. The same three program commands must begin each program
operation. All software program commands must obey the sector program timing specifications.
Power transitions will not reset the software data protection feature, however the software fea-
ture will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however, for the duration of t
WC
, a read opera-
tion will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
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0519F–FLASH–9/08
The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the
programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the
device, they are simultaneously programmed during the internal programming period. After the
first data byte has been loaded into the device, successive bytes are entered in the same man-
ner. Each new byte to be programmed must have its high to low transition on WE (or CE) within
150
s
of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
s
of the last low to high transition, the load period will end and the
internal programming period will start. A7 to A16 specify the sector address. The sector address
must be valid during each high to low transition of WE (or CE). A0 to A6 specify the byte address
within the sector. The bytes may be loaded in any order; sequential loading is not required.
4.3
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29BV010A in the following
ways: (a) V
CC
sense—if V
CC
is below 2.0V (typical), the program function is inhibited; (b) V
CC
power on delay—once V
CC
has reached the V
CC
sense level, the device will automatically time
out 10 ms (typical) before programming; (c) Program inhibit—holding any one of OE low, CE
high or WE high inhibits program cycles; and (d) Noise filter— pulses of less than 15 ns (typical)
on the WE or CE inputs will not initiate a program cycle.
4.4
Input Levels
While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs
OE,
CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can only be driven from 0 to V
CC
+ 0.6V.
4.5
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product. In
addition, users may wish to use the software product identification mode to identify the part (i.e.
using the device code), and have the system software use the appropriate sector size for pro-
gram operations. In this manner, the user can have a common board design for 256K to 4-
megabit densities and, with each density’s sector size in a memory map, have the system soft-
ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both methods of identification.
4.6
DATA Polling
The AT29BV010A features DATA polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and
the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.7
Toggle Bit
In addition to DATA polling the AT29BV010A provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.
4
AT29BV010A
0519F–FLASH–9/08
AT29BV010A
4.8
Optional Chip Erase Modes
The entire device may be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.
4.9
Boot Block Programming Lockout
The AT29BV010A has two designated memory blocks that have a programming lockout feature.
This feature prevents programming of data in the designated block once the feature has been
enabled. Each of these blocks consists of 8K bytes; the programming lockout feature can be set
independently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.
These two 8K memory sections are referred to as
boot blocks.
Secure code which will bring up a
system can be contained in a boot block. The AT29BV010A blocks are located in the first 8K
bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower addresses of memory or the higher
addresses. Once the programming lockout feature has been activated, the data in that block can
no longer be erased or programmed; data in other memory locations can still be changed
through the regular programming methods. To activate the lockout feature, a series of seven
program commands to specific addresses with specific data must be performed. Please see
Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase function will
be disabled.
4.9.1
Boot Block Lockout Detection
A software method is available to determine whether programming of either boot block section is
locked out. See Software Product Identification Entry and Exit sections. When the device is in
the software product identification mode, a read from location 00002H will show if programming
the lower address boot block is locked out while reading location 1FFF2H will do so for the upper
boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the
program lockout feature has been activated and the corresponding block cannot be pro-
grammed. The software product identification exit mode should be used to return to standard
operation.
5. Absolute Maximum Ratings*
Temperature Under Bias ............................... -55C to +125C
Storage Temperature..................................... -65C to +150C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
5
0519F–FLASH–9/08
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