Features
•
Single 2.5V or 2.7V to 3.6V Supply
•
RapidS
TM
Serial Interface: 66MHz Maximum Clock Frequency
•
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 2,048 Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (64-Kbytes)
– Chip Erase (4Mbits)
Two SRAM Data Buffers (256-, 264-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25μA Standby Current Typical
– 15μA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
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•
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•
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4-megabit
2.5-volt or
2.7-volt
DataFlash
®
AT45DB041D
(Not recommended for
new designs. Use
AT45DB041E.)
•
•
•
•
•
•
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•
1. Description
The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB041D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 4,325,376-bits of memory are organized as 2,048 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB041D also contains two
SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous data
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step read-modify-write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically
3595T–DFLASH–8/2013
reduces active pin count, facilitates hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial
and industrial applications where high-density, low-pin count, low-voltage and low-power are
essential.
To allow for simple in-system reprogrammability, the AT45DB041D does not require high input
voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V
to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the
chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),
Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2. Pin Configurations and Pinouts
Table 2-1.
Symbol
Pin Configurations
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected
and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a
high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to
end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device
will not enter the standby mode until the completion of the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from
the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK,
while output data on the SO pin is always clocked out on the falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including
command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on
the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register
will be protected against program and erase operations regardless of whether the Enable Sector Protection
command has been issued or not. The WP pin functions independently of the software controlled protection method.
After the WP pin goes low, the content of the Sector Protection Register cannot be modified.
Asserted
State
Type
CS
Low
Input
SCK
–
Input
SI
SO
–
–
Input
Output
WP
If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore
the command and perform no operation. The device will return to the idle state once the CS pin has been
deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be
recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used.
However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during
power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high
externally.
Device Power Supply: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system ground.
Low
Input
RESET
Low
Input
V
CC
GND
–
–
Power
Ground
2
AT45DB041D
3595T–DFLASH–8/2013
AT45DB041D
Figure 2-1.
MLF (VDFN)Top View
SI
SCK
RESET
CS
1
2
3
4
Figure 2-2.
SO
7
GND
6
VCC
5
WP
8
SOIC Top View
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
Note:
1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND
3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (256-/264-BYTES)
BUFFER 1 (256-/264-BYTES)
BUFFER 2 (256-/264-BYTES)
SCK
CS
RESET
VCC
GND
SI
I/O INTERFACE
SO
3
3595T–DFLASH–8/2013
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1.
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR 0a
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 0b = 248 Pages
63,488 / 65,472-bytes
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
2,048 / 2,112-bytes
PAGE ARCHITECTURE
8 Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR 0b
PAGE 6
BLOCK 30
PAGE 7
PAGE 8
PAGE 9
SECTOR 1 = 256 Pages
65,536 / 67,584-bytes
BLOCK 31
BLOCK 33
SECTOR 2 = 256 Pages
65,536 / 67,584-bytes
SECTOR 1
BLOCK 1
BLOCK 32
PAGE 14
PAGE 15
BLOCK 62
BLOCK 63
BLOCK 64
PAGE 16
PAGE 17
PAGE 18
SECTOR 6 = 256 Pages
65,536 / 67,584-bytes
BLOCK 65
SECTOR 7 = 256 Pages
65,536 / 67,584-bytes
BLOCK 254
BLOCK 255
PAGE 2,046
PAGE 2,047
Block = 2,048 / 2,112-bytes
Page = 256 / 264-bytes
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in
Tables 15-1 through 15-7.
A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer
or main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most significant
bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264-bytes) is referenced in the data-
sheet using the terminology BEA8 - BFA0 to denote the nine address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to desig-
nate a page address and BA8 - BA0 denotes the nine address bits required to designate a byte
address within the page.
For the “Power of 2” binary page size (256-bytes), the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the eight address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to desig-
nate a page address and A7 - A0 denotes the eight address bits required to designate a byte
address within a page.
4
AT45DB041D
3595T–DFLASH–8/2013
AT45DB041D
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and
Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for
details on the clock cycle sequences for each mode.
6.1
Continuous Array Read (Legacy Command – E8H): Up to 66MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (264-bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes.
The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main
memory array to read, and the last nine bits (BA8 - BA0) of the 20-bit address sequence specify
the starting byte address within the page. To perform a continuous read from the binary page
size (256-bytes), the opcode (E8H) must be clocked into the device followed by three address
bytes and four don’t care bytes. The first 11 bits (A18 - A8) of the 19-bits sequence specify which
page of the main memory array to read, and the last 8 bits (A7 - A0) of the 19-bits address
sequence specify the starting byte address within the page. The don’t care bytes that follow the
address bytes are needed to initialize the read operation. Following the don’t care bytes, addi-
tional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with cross-
ing over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by
the f
CAR1
specification. The Continuous Array Read bypasses both data buffers and leaves the
contents of the buffers unchanged.
6.2
Continuous Array Read (High Frequency Mode – 0BH): Up to 66MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by f
CAR1
. To perform a
continuous read array with the page size set to 264-bytes, the CS must first be asserted then an
opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the
main memory array to read, and the last nine bits (BA8 - BA0) of the 20-bit address sequence
specify the starting byte address within the page. To perform a continuous read with the page
size set to 256-bytes, the opcode, 0BH, must be clocked into the device followed by three
address bytes (A18 - A0) and a dummy byte. Following the dummy byte, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
5
3595T–DFLASH–8/2013
