AT45DB641E
64-Mbit DataFlash (with Extra 2-Mbits), 1.7V Minimum
SPI Serial Flash Memory
Features
Single 1.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidS
™
operation
Continuous read capability through entire array
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (t
V
) of 8ns maximum
User configurable page size
256 bytes per page
264 bytes per page (default)
Page size can be factory pre-configured for 256 bytes
Two fully independent SRAM data buffers (256/264 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
Byte/Page Program (1 to 256/264 bytes) directly into main memory
Buffer Write | Buffer to Main Memory Page Program
Flexible erase options
Page Erase (256/264 bytes)
Block Erase (2KB)
Sector Erase (256KB)
Chip Erase (64-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
400nA Ultra-Deep Power-Down current (typical)
5µA Deep Power-Down current (typical)
25µA Standby current (typical)
7mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
8-pad Very-thin DFN (6 x 8 x 1.0mm)
9-ball BGA (6mm x 6mm package, 3 x 3 ball array)
44-ball dBGA (6 x 8 modified ball array)
Die in Wafer Form
DS-45DB641E-027J–DFLASH–8/2017
Description
The AT45DB641E is a 1.7V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of
digital voice, image, program code, and data storage applications. The AT45DB641E also supports the RapidS serial
interface for applications requiring very high speed operation. Its 69,206,016 bits of memory are organized as 32,768
pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB641E also contains two SRAM
buffers of 256/264 bytes each. Interleaving between both buffers can dramatically increase a system's ability to write a
continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and
E
2
PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write
operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash
®
uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces
active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and
reduces package size. The device is optimized for use in many commercial and industrial applications where
high-density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, the AT45DB641E does not require high input voltages for
programming. The device operates from a single 1.7V to 3.6V power supply for the erase and program and read
operations. The AT45DB641E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting
of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
1.
Pin Configurations and Pinouts
Figure 1-1. Pinouts
8-lead SOIC
Top View
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
8-pad UDFN
Top View
(through package)
9-ball UBGA
Top View
(through package)
SO
GND
V
CC
WP
SI
SCK
RESET
CS
1
2
3
4
SO
7
GND
6
V
CC
5
WP
8
SCK
GND
V
CC
CS
NC
WP
SO
SI
RST
44-ball dBGA
Top View
1
2
3
4
5
6
Note:
1.
A
(NC)
(NC)
(NC)
(NC)
(NC)
The metal pad on the bottom of the DFN package is not internally
connected to a voltage potential.This pad can be a “no connect”
or connected to GND. Care must be taken to avoid the Metal Pad
shorting on PCB tracks.
B
(NC)
SI
RST
CS
(NC)
C
(NC)
SI
SCK
RST
CS
(NC)
D
(NC)
SI
SCK
RST
CS
(NC)
E
(NC)
SO
GND
Vcc
WP
(NC)
F
(NC)
SO
GND
Vcc
WP
(NC)
G
(NC)
SO
Vcc
WP
(NC)
H
(NC)
(NC)
(NC)
(NC)
(NC)
AT45DB641E
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Table 1-1.
Pin Configurations
Asserted
State
Symbol
Name and Function
Chip Select:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not Deep Power-Down
mode) and the output pin (SO) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
Serial Clock:
This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is
always latched on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
Serial Input:
The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS
is deasserted).
Serial Output:
The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state
whenever the device is deselected (CS is deasserted).
Write Protect:
When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of
whether the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
contents of the Sector Protection Register cannot be modified.
Type
CS
Low
Input
SCK
—
Input
SI
—
Input
SO
—
Output
WP
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle
state once the CS pin has been deasserted. The Enable Sector Protection command and the
Sector Lockdown command, however, will be recognized by the device when the WP pin is
asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected to
V
CC
whenever possible.
Reset:
A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin
is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature is not utilized, then it is
recommended that the RESET pin be driven high externally.
Low
Input
RESET
Low
Input
V
CC
GND
Device Power Supply:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Ground:
The ground reference for the power supply. GND should be connected to the system
ground.
—
—
Power
Ground
AT45DB641E
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2.
Block Diagram
Figure 2-1. Block Diagram
WP
Flash Memory Array
Page (256/264 bytes)
Buffer 1 (256/264 bytes)
Buffer 2 (256/264 bytes)
SCK
CS
RESET
V
CC
GND
SI
I/O Interface
SO
AT45DB641E
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3.
Memory Array
To provide optimal flexibility, the AT45DB641E memory array is divided into three levels of granularity comprising of
sectors, blocks, and pages.
Figure 3-1, Memory Architecture Diagram
illustrates the breakdown of each level and details
the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at
the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page
level.
Figure 3-1. Memory Architecture Diagram
Sector Architecture
Sector 0a = 8 pages
2,048 / 2,112 bytes
Block Architecture
Sector 0a
Block 0
Block 1
Block 2
Page Architecture
8 Pages
Page 0
Page 1
Sector 0b = 1,016 pages
260,096 / 268,224 bytes
Sector 0b
Block 0
Page 6
Block 126
Page 7
Page 8
Page 9
Sector 1 = 1,024 pages
262,144 / 270,336 bytes
Block 127
Block 129
Sector 2 = 1,024 pages
262,144 / 270,336 bytes
Sector 1
Block 1
Block 128
Page 14
Page 15
Block 254
Block 255
Block 256
Page 16
Page 17
Page 18
Sector 30 = 1,024 pages
262,144 / 270,336 bytes
Block 257
Sector 31 = 1,,024 pages
262,144 / 270,336 bytes
Block 4,094
Block 4,095
Page 32,766
Page 32,767
Block = 2,048 / 2,112 bytes
Page = 256 / 264 bytes
AT45DB641E
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