Features
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Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 110 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30
µ
s/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50
µ
A CMOS Standby Current
•
Typical 10,000 Write Cycles
Description
The AT49BV/LV008 is a 3-volt-only in-system Flash Memory device. Its 8 megabits of
memory is organized as 1,024,576 words by 8 bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 110 ns
with power dissipation of just 90 mW over the commercial temperature range. When
the device is deselected, the CMOS standby current is less than 50
µA.
8-Megabit
(1M x 8)
3-volt Only
Flash Memory
AT49BV008
AT49LV008
(continued)
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Data Inputs/Outputs
No Connect
TSOP Top VIew
Type 1
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
A19
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0
AT49BV/LV008
8-Megabit 1M x
8 3-volt Only
Rev. 1043A–03/98
1
To allow for simple in-system reprogrammability, the
AT49BV/LV008 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV008 is performed by eras-
ing the entire 8 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming time
is a fast 30
µs.
The end of a program cycle can be option-
ally detected by the DATA polling feature. Once the end of
a byte program cycle has been detected, a new access for
a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
V
CC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
FFFFFH
X DECODER
MAIN MEMORY
(1008K BYTES)
03FFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
00000H
Y DECODER
ADDRESS
INPUTS
Device Operation
READ:
The AT49BV/LV008 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE:
Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
2
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the
AT49BV/LV008 boot block is 00000H to 03FFFH.
AT49BV/LV008
AT49BV/LV008
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12V
±
0.5V. By doing this, pro-
tected boot block data can be altered through a chip erase,
or byte programming. When the RESET pin is brought back
to TTL levels, the boot block programming lockout feature
is again active.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49BV/LV008 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT:
In addition to DATA polling, the
AT49BV/LV008 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
RDY/BUSY:
An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR - tying of several devices to the same
RDY/BUSY line.
RESET:
A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation, puts the
outputs of the device in a high impedance state, and
reduces the current drawn by the part to a minimum. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V
±
0.5V input signal to the
RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT49BV/LV008
in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
3
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Byte Program
Boot Block Lockout
(1)
Product ID Entry
Product ID Exit
(2)
Product ID Exit
(2)
Notes:
Bus
Cycles
1
6
4
6
3
3
1
1st Bus
Cycle
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
D
OUT
AA
AA
AA
AA
AA
F0
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
D
IN
AA
2AAA
55
5555
40
2AAA
55
5555
10
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
1. The 16K byte boot sector has the address range 00000H to 03FFFH.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4
AT49BV/LV008
AT49BV/LV008
DC and AC Operating Range
AT49LV008-11
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
3.0V - 3.6V
AT49BV/LV008-12
0°C - 70°C
-40°C - 85°C
2.7V - 3.6V/3.0V - 3.6V
AT49BV008-15
0°C - 70°C
-40°C - 85°C
2.7V - 3.6V
Operating Modes
Mode
Read
Program
(2)
Standby/Write
Inhibit
Program Inhibit
Program Inhibit
Output Disable
RESET
Product Identification
V
IL
Hardware
V
IL
V
IH
V
IH
A1 - A19 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A19 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
A0 = V
IL
, A1 - A19 = V
IL
A0 = V
IH
, A1 - A19 = V
IL
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
CE
V
IL
V
IL
V
IH
X
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
X
WE
V
IH
V
IL
X
V
IH
X
X
X
RESET
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
X
High Z
High Z
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
RDY/BUSY
V
OH
V
OL
V
OH
V
OH
V
OH
V
OH
Software
(5)
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V
4. Manufacturer Code: 1FH
Device Code: 22H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
I
LI
I
LO
I
PD
I
SB1
I
SB2
I
CC(1)
V
IL
V
IH
V
OL
V
OH1
Parameter
Input Load Current
Output Leakage Current
Power Down Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1 mA
I
OH
= -400
µA
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
RESET = GND
±
0.2V
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Min
Max
1
1
50
50
1
25
0.6
Units
µA
µA
µA
µA
mA
mA
V
V
V
V
Note:
1. I
CC
in the erase mode is 50 mA.
5
