Features
•
Conforms to Intel LPC Interface Specification 1.0
•
8M Bits of Flash Memory for Platform Code/Data Storage
•
– Automated Byte-program and Sector-erase Operations
Two Configurable Interfaces
– Low Pin Count (LPC) Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
Low Pin Count Hardware Interface Mode
– 5-signal Communication Interface Supporting x8 Reads and Writes
– Read and Write Protection for Each Sector Using Software-controlled Registers
– Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other
Sectors
– Five General-purpose Inputs, GPIs, for Platform Design Flexibility
– Operates with 33 MHz PCI Clock and 3.3V I/O
Address/Address Multiplexed (A/A Mux) Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Supports Fast On-board or Out-of-system Programming
Power Supply Specifications
– V
CC
: 3.3V ± 0.3V
– V
PP
: 3.3V and 12V for Fast Programming
Industry-standard Package
– 40-lead TSOP or 32-lead PLCC
•
•
•
•
8-megabit
Low-pin Count
Flash Memory
AT49LL080
Description
The AT49LL080 is a Flash memory device designed to interface with the LPC bus for
PC Applications. A feature of the AT49LL080 is the nonvolatile memory core. The
high-performance memory is arranged in sixteen sectors (see page 11).
The AT49LL080 supports two hardware interfaces: Low Pin Count (LPC) for in-system
operation and Address/Address Multiplexed (A/A Mux) for programming during manu-
facturing. The IC (Interface Configuration) pin of the device provides the control
between the interfaces. The interface mode needs to be selected prior to power-up or
before return from reset (RST or INIT low to high transition).
Pin Configuration
PLCC
GPI2 [A8]
GPI3 [A9]
RST [RST]
VPP [VPP]
VCC [VCC]
CLK [R/C]
GPI4 [A10]
(NC) CE
[IC (V
IH
)] IC (V
IL
)
[NC] NC
[NC] NC
[NC] NC
[NC] NC
[A10] GPI4
[NC] NC
[R/C] CLK
[VCC] VCC
[VPP] VPP
[RST] RST
[NC] NC
[NC] NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP, Type I
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GNDa [GNDa]
VCCa [VCCa]
LFRAME [WE]
INIT [OE]
RFU [RY/BY]
RFU [I/O7]
RFU [I/O6]
RFU [I/O5]
RFU [I/O4]
VCC [VCC]
GND [GND]
GND [GND]
LAD3 [I/O3]
LAD2 [I/O2]
LAD1 [I/O1]
LAD0 [I/O0]
NC [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
[I/O1] LAD1
[I/O2] LAD2
[GND] GND
[I/O3] LAD3
[I/O4] RFU
[I/O5] RFU
[I/O6] RFU
14
15
16
17
18
19
20
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] NC
[I/O0] LAD0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
IC (V
IL
) [IC(V
IH
)]
CE [NC]
NC
NC
VCC [VCC]
INIT [OE]
LFRAME [WE]
RFU [RY/BY]
RFU [I/O7]
[ ] Designates A/A Mux Mode
[ ] Designates A/A Mux Mode
Rev. 3273C–FLASH–5/03
1
An internal Command User Interface (CUI) serves as the control center between the two
device interfaces (LPC and A/A Mux) and internal operation of the nonvolatile memory.
A valid command sequence written to the CUI initiates device automation.
Specifically designed for 3V systems, the AT49LL080 supports read operations at 3.3V
and sector erase and program operations at 3.3V and 12V V
PP
. The 12V V
PP
option ren-
ders the fastest program performance which will increase factory throughput, but is not
recommended for standard in-system LPC operation in the platform. Internal V
PP
detec-
tion circuitry automatically configures the device for sector erase and program
operations. Note that, while current for 12V programming will be drawn from V
PP
, 3.3V
programming board solutions should design such that V
PP
draws from the same supply
as V
CC
, and should assume that full programming current may be drawn from either pin.
Low Pin Count Interface
The Low Pin Count (LPC) interface is designed to work with the I/O Controller Hub (ICH)
during platform operation.
The LPC interface consists primarily of a five-signal communication interface used to
control the operation of the device in a system environment. The buffers for this inter-
face are PCI compliant. To ensure the effective delivery of security and manageability
features, the LPC interface is the only way to get access to the full feature set of the
device. The LPC interface is equipped to operate at 33 MHz, synchronous with the PCI
bus.
Address/Address
Multiplexed Interface
The A/A Mux interface is designed as a programming interface for OEMs to use during
motherboard manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with
automated test equipment (ATE) and PROM programmers in the OEM’s manufacturing
flow. This interface also allows the device to have an efficient programming interface
with potentially large future densities, while still fitting into a 32-pin package. Only basic
reads, programming, and erase of the nonvolatile memory sectors can be performed
through the A/A Mux interface. In this mode LPC features, security features and regis-
ters are unavailable. A row/column (R/C) pin determines which set of addresses “rows
or columns” are latched.
Block Diagram
CE
WP
TBL
GPI (4:0)
ID (3:1)
LAD (3:0)
LFRAME
CLK
INIT
OE
R/C
WE
RY/BY
A10 - A0
I/O7 - I/O0
RST
IC
A/A MUX
INTERFACE
LPC
INTERFACE
FLASH
ARRAY
CONTROL
LOGIC
2
AT49LL080
3273C–FLASH–5/03
AT49LL080
Pin Description
Table 1 details the usage of each of the device pins. Most of the pins have dual function-
ality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux
functionality for pins is shown in
bold
in the description box for that pin. All pins are
designed to be compliant with voltage of V
CC
+ 0.3V max, unless otherwise noted.
Table 1.
Pin Description
Interface
Symbol
IC
Type
INPUT
LPC
X
A/A Mux
X
Name and Function
INTERFACE CONFIGURATION PIN:
This pin determines which interface is
operational. This pin is held high to enable the A/A Mux interface. This pin is
held low to enable the LPC interface. This pin must be set at power-up or before
return from reset and not changed during device operation. This pin is pulled
down with an internal resistor, with values between 20 and 100 kΩ. With IC high
(A/A Mux mode), this pin will exhibit a leakage current of approximately 200 µA.
This pin may be floated, which will select LPC mode.
INTERFACE RESET:
Valid for both A/A Mux and LPC interface operations.
When driven low, RST inhibits write operations to provide data protection during
power transitions, resets internal automation, and tri-states pins LAD[3:0] (in
LPC interface mode). RST high enables normal operation. When exiting from
reset, the device defaults to read array mode.
PROCESSOR RESET:
This is a second reset pin for in-system use. This pin is
internally combined with the RST pin. If this pin or RST is driven low, identical
operation is exhibited. This signal is designed to be connected to the chipset
INIT signal (Max voltage depends on the processor. Do not use 3.3V.)
A/A Mux =
OE
33 MHz CLOCK for LPC INTERFACE:
This input is the same as the PCI clock
and adheres to the PCI specification.
A/A Mux =
R/C
ADDRESS AND DATA:
These pins provide LPC control signals, as well as
addresses and command Inputs/Outputs Data.
A/A Mux = I/O[3:0]
FRAME:
This pin indicates the start of a data transfer operation; also used to
abort an LPC cycle in progress.
A/A Mux =
WE
IDENTIFICATION INPUTS:
These three pins are part of the mechanism that
allows multiple parts to be attached to the same bus. The strapping of these
pins is used to identify the component. The boot device must have ID[3:1] =
000, and it is recommended that all subsequent devices should use a
sequential up-count strapping (i.e., 001, 010, 011, etc.). These pins are pulled
down with internal resistors, with values between 20 and 100 kΩ when in LPC
mode. Any ID pins that are pulled high will exhibit a leakage current of
approximately 200 µA. Any pins intended to be low may be left to float. In a
single LPC system, all may be left floating.
A/A Mux = A[3:0]
When CE is low, the device is enabled. This pin is pulled down with an
internal resistor and can exhibit a leakage current of approximately 10 µA.
Since this pin is internally pulled down and thus can be left unconnected, the
AT49LL080 is compatible with systems that do not use a CE signal. To reduce
power, the device is placed in a low-power standby mode when CE is high.
RST
INPUT
X
X
INIT
INPUT
X
CLK
INPUT
X
LAD[3:0]
I/O
X
LFRAME
INPUT
X
ID[3:1]
INPUT
X
CE
INPUT
X
3
3273C–FLASH–5/03
Table 1.
Pin Description (Continued)
Interface
Symbol
GPI[4:0]
Type
INPUT
LPC
X
A/A Mux
Name and Function
GENERAL PURPOSE INPUTS:
These individual inputs can be used for
additional board flexibility. The state of these pins can be read through LPC
registers. These inputs should be at their desired state before the start of the
PCI clock cycle during which the read is attempted, and should remain at the
same level until the end of the read cycle. They may
only
be used for
3.3V
signals. Unused GPI pins must
not
be floated.
A/A Mux = A[10:6]
TOP SECTOR LOCK:
When low, prevents programming or sector erase to the
highest addressable sector (15), regardless of the state of the lock registers
TBL high disables hardware write protection for the top sector, though register-
based protection still applies. The status of TBL does not affect the status of
sector-locking registers.
A/A Mux = A4
WRITE-PROTECT:
When low, prevents programming or sector erase to all but
the highest addressable sectors (0 - 14), regardless of the state of the
corresponding lock registers. WP-high disables hardware write protection for
these sectors, though register-based protection still applies. The status of TBL
does not affect the status of sector-locking registers.
A/A Mux = A5
X
LOW-ORDER ADDRESS INPUTS:
Inputs for low-order addresses during read
and write operations. Addresses are internally latched during a write cycle. For
the A/A Mux interface these addresses are latched by R/C and share the same
pins as the high-order address inputs.
DATA INPUT/OUTPUTS:
These pins receive data and commands during write
cycles and transmit data during memory array and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
OUTPUT ENABLE:
Gates the device’s outputs during a read cycle.
ROW-COLUMN ADDRESS SELECT:
For the A/A Mux interface, this pin
determines whether the address pins are pointing to the row addresses,
A0 - A10, or to the column addresses, A11 - A19.
WRITE ENABLE:
Controls writes to the array sectors. Addresses and data are
latched on the rising edge of the WE pulse.
SECTOR ERASE/PROGRAM POWER SUPPLY:
For erasing array sectors or
programming data 0V < V
PP
< 3.6V or 12V for faster erase and programming
operations. The VPP pin can be left unconnected. Sector erase or program with
an invalid V
PP
(see DC Characteristics) produces spurious results and should
not be attempted. V
PP
may only be held at 12V for 80 hours over the lifetime of
the device.
DEVICE POWER SUPPLY:
Internal detection automatically configures the
device for optimized read performance. Do no float any power pins. With V
CC
≤
V
LKO
, all write attempts to the flash memory are inhibited. Device operations at
invalid V
CC
voltages (see DC Characteristics) produce spurious results and
should not be attempted.
GROUND:
Do not float any ground pins.
ANALOG POWER SUPPLY:
This supply should share the same system supply
as V
CC
.
TBL
INPUT
X
WP
INPUT
X
A0 - A10
INPUT
I/O0 - I/O7
I/O
X
OE
R/C
INPUT
INPUT
X
X
WE
V
PP
INPUT
SUPPLY
X
X
X
V
CC
SUPPLY
X
X
GND
V
CCa
SUPPLY
SUPPLY
X
X
X
X
4
AT49LL080
3273C–FLASH–5/03
AT49LL080
Table 1.
Pin Description (Continued)
Interface
Symbol
GNDa
RFU
Type
SUPPLY
LPC
X
X
A/A Mux
X
Name and Function
ANALOG GROUND:
Should be tied to same plane as GND.
RESERVED FOR FUTURE USE:
These pins are reserved for future
generations of this product and should be connected accordingly. These pins
may be left disconnected or driven. If they are driven, the voltage levels should
meet V
IH
and V
IL
requirements.
A/A Mux = I/O[7:4]
X
X
NO CONNECT:
Pin may be driven or floated. If it is driven, the voltage levels
should meet V
IH
and V
IL
.
READY/BUSY:
Valid only in A/A Mux Mode. This output pin is a reflection of bit
7 in the status register. This pin is used to determine sector erase or program
completion.
NC
RY/BY
OUTPUT
X
Low Pin Count
Interface (LPC)
Table 2 lists the seven required signals used for the LPC interface.
Table 2.
LPC Required Signal List
Direction
Signal
LAD[3:0]
LFRAME
RST
Peripheral
I/O
I
I
Master
I/O
O
I
Description
Multiplexed command, address and data
Indicates start of a new cycle, termination of broken
cycle.
Reset: Same as PCI Reset on the master. The master
does not need this signal if it already has PCIRST on its
interface.
Clock: Same 33 MHz clock as PCI clock on the master.
Same clock phase with typical PCI skew. The master
does not need this signal if it already has PCICLK on its
interface.
CLK
I
I
LAD[3:0]:
The LAD[3:0] signal lines communicate address, control, and data informa-
tion over the LPC bus between a master and a peripheral. The information
communicated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), trans-
fer direction (read/write), address, data, wait states, DMA channel, and bus master
grant.
LFRAME:
LFRAME is used by the master to indicate the start of cycles and the termina-
tion of cycles due to an abort or time-out condition. This signal is to be used be by
peripherals to know when to monitor the bus for a cycle.
The LFRAME signal is used as a general notification that the LAD[3:0] lines contain
information relative to the start or stop of a cycle, and that peripherals must monitor the
bus to determine whether the cycle is intended for them. The benefit to peripherals of
LFRAME is, it allows them to enter lower power states internally.
When peripherals sample LFRAME active, they are to immediately stop driving the
LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information.
RESET:
RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low
deselects the memory, places output drivers in a high-impedance state, and turns off all
5
3273C–FLASH–5/03
