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Features

•

Single Supply for Read and Write: 2.7V to 3.3V (BV), 3.0V to 3.3V (LV)

•

Access Time – 90 ns

•

Sector Erase Architecture

Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout

Two 16K Word (32K Byte) Sectors with Individual Write Lockout

Two 8K Word (16K Byte) Sectors with Individual Write Lockout

Four 4K Word (8K Byte) Sectors with Individual Write Lockout

Fast Word Program Time – 20 µs

Fast Sector Erase Time – 200 ms

Dual Plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors

Memory Plane B: Fourteen 32K Word Sectors

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

Low-power Operation

– 25 mA Active

– 10 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

Optional VPP Pin for Fast Programming

RESET Input for Device Initialization

Sector Program Unlock Command

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

•

8-megabit

(512K x 16/1M x 8)

3-volt Only

Flash Memory

AT49BV8011

AT49BV8011T

AT49LV8011

AT49LV8011T

Description

The AT49BV/LV8011(T) is a 2.7- to 3.3-volt 8-megabit Flash memory organized as

524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data

appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided

into 22 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball

CBGA packages. The device has CE, and OE control signals to avoid any bus

Pin Configurations

Pin Name

A0 - A18

RESET

RDY/BUSY

VPP

I/O0 - I/O14

I/O15 (A-1)

BYTE

VCCQ

(continued)

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Optional Power Supply for Faster

Program/Erase Operations

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Output Power Supply

Rev. 1265E–01/00

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

RESET

VPP

RDY/BUSY

A18

A17

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

CBGA Top View

A7 RDY/BUSY WE

A17

I/O0

I/O8

I/O9

I/O1

A18

I/O2

I/O10

I/O11

I/O3

RESET

VPP

I/O5

I/O12

VCC

I/O4

A10

A11

I/O7

I/O14

I/O13

I/O6

A13

A12

A14

A15

A16

BYTE

I/O15

/A-1

VSS

contention. This device can be read or reprogrammed

using a single 2.7V power supply, making it ideally suited

for in-system programming.

The device powers on in the read mode. Command

sequences are used to place the device in other operation

modes such as Program and Erase. The device has the

capability to protect the data in any sector. Once the data

protection for a given sector is enabled, the data in that

sector cannot be changed using input levels between

ground and V

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while pro-

gram or erase functions are being executed in memory

plane A and vice versa. This operation allows improved

system performance by not requiring the system to wait for

a program or erase operation to complete before a read is

performed. To further increase the flexibility of the device, it

contains an Erase Suspend feature. This feature will put

the Erase on hold for any amount of time and let the user

read data from or program data to any of the remaining

sectors within the same memory plane. There is no reason

to suspend the erase operation if the data to be read is in

the other memory plane. The end of a program or an Erase

cycle is detected by the Ready/Busy pin, Data polling, or by

the toggle bit.

A VPP pin is provided to improve program/erase times.

This pin can be tied to V

. To take advantage of faster

programming and erasing, the pin should supply 4.5 to

5.5 volts during program and erase operations.

A 6-byte command (bypass unlock) sequence to remove

the requirement of entering the 3-byte program sequence

is offered to further improve programming time. After enter-

ing the 6-byte code, only single pulses on the write control

lines are required for writing into the device. This mode

(single-pulse byte/word program) is exited by powering

down the device, or by pulsing the RESET pin low for a

minimum of 50 ns and then bringing it back to V

. Erase

and Erase Suspend/Resume commands will not work while

in this mode; if entered they will result in data being pro-

grammed into the device. It is not recommended that the

6-byte code reside in the software of the final product but

only exist in external programming code.

The BYTE pin controls whether the device data I/O pins

operate in the byte or word configuration. If the BYTE pin is

set at logic “1”, the device is in word configuration,

I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte con-

figuration, and only data I/O pins I/O0 - I/O7 are active and

controlled by CE and OE. The data I/O pins I/O8 - I/O14

are tri-stated, and the I/O15 pin is used as an input for the

LSB (A-1) address function.

AT49BV/LV8011(T)

AT49BV/LV8011(T)

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

OUTPUT

MULTIPLEXER

A0 - A18

INPUT

BUFFER

DATA

IDENTIFIER

STATUS

COMMAND

ADDRESS

LATCH

DATA

COMPARATOR

RESET

BYTE

RDY/BUSY

WRITE STATE

MACHINE

Y-DECODER

Y-GATING

PROGRAM/ERASE

VOLTAGE SWITCH

VPP

VCC

GND

X-DECODER

PLANE B

SECTORS

PLANE A SECTORS

Device Operation

READ:

The AT49BV/LV8011(T) is accessed like an

EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the

address pins are asserted on the outputs. The outputs are

put in the high impedance state whenever CE or OE is

high. This dual line control gives designers flexibility in pre-

venting bus contention.

COMMAND SEQUENCES:

When the device is first pow-

ered on it will be reset to the read or standby mode,

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table

(I/O8 - I/O15 are don’t care inputs for the command codes).

The command sequences are written by applying a low

pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address

locations used in the command sequences are not affected

by entering the command sequences.

RESET:

A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high impedance state. When

a high level is reasserted on the RESET pin, the device

returns to the read or standby mode, depending upon the

state of the control inputs. By applying a 12V

0.5V input

signal to the RESET pin, any sector can be reprogrammed

even if the sector lockout feature has been enabled (see

“Sector Programming Lockout Override” section).

ERASURE:

Before a byte/word can be reprogrammed, it

must be erased. The erased state of memory bits is a logi-

cal “1”. The entire device can be erased by using the Chip

Erase command or individual sectors can be erased by

using the Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one time

by using the 6-byte chip erase software code. After the chip

erase has been initiated, the device will internally time the

erase operation so that no external clocks are required.

The maximum time to erase the chip is t

If the sector lockout has been enabled, the Chip Erase will

not erase the data in the sector that has been locked; it will

erase only the unprotected sectors. After the chip erase,

the device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the

device is organized into 22 sectors that can be individually

erased. The Sector Erase command is a six bus cycle

operation. The sector address is latched on the falling WE

edge of the sixth cycle while the 30H Data Input command

is latched on the rising edge of WE. The sector erase starts

after the rising edge of WE of the sixth cycle. The erase

operation is internally controlled; it will automatically time to

completion. The maximum time to erase a section is t

SEC

When the sector programming lockout feature is not

enabled, the sector will erase (from the same Sector Erase

command). Once a sector has been protected, data in the

protected sectors cannot be changed unless the RESET

pin is taken to 12V ± 0.5V. An attempt to erase a sector

that has been protected will result in the operation terminat-

ing in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is

erased, it is programmed (to a logical “0”) on a byte-by-byte

or on a word-by-word basis. Programming is accomplished

via the internal device command register and is a four bus

cycle operation. The device will automatically generate the

required internal program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

the specified t

cycle time. The DATA polling feature or

the toggle bit feature may be used to indicate the end of a

program cycle.

SECTOR PROGRAMMING LOCKOUT:

Each sector has a

programming lockout feature. This feature prevents pro-

gramming of data in the designated sectors once the

feature has been enabled. These sectors can contain

secure code that is used to bring up the system. Enabling

the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This

feature does not have to be activated; any sector’s usage

as a write-protected region is optional to the user.

Once the feature is enabled, the data in the protected sec-

tors can no longer be erased or programmed when input

levels of 5.5V or less are used. Data in the remaining

sectors can still be changed through the regular program-

ming method. To activate the lockout feature, a series of

six program commands to specific addresses with specific

data must be performed. Please refer to the Command

Definitions table.

SECTOR LOCKOUT DETECTION:

A software method is

available to determine if programming of a sector is locked

out. When the device is in the software product identifica-

tion mode (see “Software Product Identification Entry/Exit”

sections), a read from address location 00002H within a

sector will show if programming the sector is locked out. If

the data on I/O0 is low, the sector can be programmed; if

the data on I/O0 is high, the program lockout feature has

been enabled and the sector cannot be programmed. The

software product identification exit code should be used to

return to standard operation.

SECTOR PROGRAMMING LOCKOUT OVERRIDE:

The

user can override the sector programming lockout by taking

the RESET pin to 12V ± 0.5V. By doing this, protected data

can be altered through a chip erase, sector erase or

byte/word programming. When the RESET pin is brought

back to TTL levels, the sector programming lockout feature

is again active.

ERASE SUSPEND/ERASE RESUME:

The Erase Sus-

pend command allows the system to interrupt a sector

erase operation and then program or read data from a dif-

ferent sector within the same plane. Since this device has a

dual plane architecture, there is no need to use the erase

suspend feature while erasing a sector when you want to

read data from a sector in the other plane. After the Erase

Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After

the erase operation has been suspended, the plane that

contains the suspended sector enters the erase-suspend-

read mode. The system can then read data or program

data to any other sector within the device. An address is

not required during the Erase Suspend command. During a

sector erase suspend, another sector cannot be erased. To

resume the sector erase operation, the system must write

the Erase Resume command. The Erase Resume com-

mand is a one bus cycle command that does require the

plane address, which is determined by A18 - A16. The

device also supports an erase suspend during a complete

chip erase. While the chip erase is suspended, the user

can read from any sector within the memory that is pro-

tected. The command sequence for a chip erase suspend

and a sector erase suspend are the same.

PRODUCT IDENTIFICATION:

The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

AT49BV/LV8011(T)

AT49BV/LV8011(T)

For details, see “Operating Modes” (for hardware opera-

tion) or “Software Product Identification”. The manufacturer

and device code is the same for both modes.

DATA POLLING:

The AT49BV/LV8011(T) features DATA

polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte/word loaded

will result in the complement of the loaded data on I/O7.

Once the program cycle has been completed, true data is

valid on all outputs and the next cycle may begin. During a

chip or sector erase operation, an attempt to read the

device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device.

DATA polling may begin at any time during the program

cycle. Please see “Status Bit Table” for more details.

TOGGLE BIT:

In addition to DATA polling, the

AT49BV/LV8011(T) provides another method for determin-

ing the end of a program or erase cycle. During a program

or erase operation, successive attempts to read data from

the same memory plane will result in I/O6 toggling between

“1” and “0”. Once the program cycle has completed, I/O6

will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be

used in conjunction with the toggle bit that is available on

I/O6. While a sector is erase suspended, a read or a

program operation from the suspended sector will result in

the I/O2 bit toggling. Please see “Status Bit Table” for more

details.

RDY/BUSY:

An open drain READY/BUSY output pin pro-

vides another method of detecting the end of a program or

erase operation. RDY/BUSY is actively pulled low during

the internal program and erase cycles and is released at

the completion of the cycle. The open drain connection

allows for OR-tying of several devices to the same

RDY/BUSY line.

HARDWARE DATA PROTECTION:

Hardware features

protect against inadvertent programs to the

AT49BV/LV8011(T) in the following ways: (a) V

sense: if

is below 1.8V (typical), the program function is inhib-

ited. (b) V

power on delay: once V

has reached the

sense level, the device will automatically time out

10 ms (typical) before programming. (c) Program inhibit:

holding any one of OE low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.3V

power supply, the address inputs and control inputs (OE,

CE, and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V

+ 0.6V.