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Features

•

Low Voltage Operation

•

– 2.7V Read

– 5V Program/Erase

Fast Read Access Time - 120 ns

Internal Erase/Program Control

Sector Architecture

– One 8K Words (16K bytes) Boot Block with Programming Lockout

– Two 8K Words (16K bytes) Parameter Blocks

– One 488K Words (976K bytes) Main Memory Array Block

Fast Sector Erase Time - 10 seconds

Word-By-Word Programming - 30

µs/Word

Hardware Data Protection

DATA Polling For End Of Program Detection

Low Power Dissipation

– 25 mA Active Current

– 50

µA

CMOS Standby Current

Typical 10,000 Write Cycles

•

8-Megabit

(512K x 16)

CMOS Flash

Memory

AT49BV8192

AT49BV8192T

AT49LV8192

AT49LV8192T

Description

The AT49BV8192 and AT49LV8192 are 3-volt, 8-megabit Flash Memories organized

as 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile

CMOS technology, the devices offer access times to 120 ns with power dissipation of

just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50

µA.

(continued)

Pin Configurations

Pin Name

A0 - A18

RESET

I/O0 - I/O15

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

Program/Erase Power

Supply

Data

Inputs/Outputs

No Connect

TSOP Top View

Type 1

A15

A13

A11

A14

A12

A10

I/O15

I/O14

I/O13

I/O12

VCC

I/O3

I/O2

I/O1

I/O0

GND

A16

GND

I/O7

I/O6

I/O5

I/O4

I/O11

I/O10

I/O9

I/O8

SOIC (SOP)

VPP

A18

A17

GND

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

RESET

A10

A11

A12

A13

A14

A15

A16

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

RESET

VPP NC

A18

A17

0978B-A–11/97

The device contains a user-enabled “boot block” protection

feature. Two versions of the feature are available: the

AT49BV/LV8192 locates the boot block at lowest order

addresses (“bottom boot”); the AT49BV/LV8192T locates it

at highest order addresses (“top boot”)

To allow for simple in-system reprogrammability, the

AT49BV/LV8192 does not require high input voltages for

programming. Reading data out of the device is similar to

reading from an EPROM; it has standard CE, OE, and WE

inputs to avoid bus contention. Reprogramming the

AT49BV/LV8192 is performed by first erasing a block of

data and then programming on a word-by-word basis.

The device is erased by executing the erase command

sequence; the device internally controls the erase opera-

tion. The memory is divided into three blocks for erase

operations. There are two 8K word parameter block sec-

tions and one sector consisting of the boot block and the

main memory array block. The AT49BV/LV8192 is pro-

grammed on a word-by-word basis.

The device has the capability to protect the data in the boot

block; this feature is enabled by a command sequence.

Once the boot block programming lockout feature is

enabled, the data in the boot block cannot be changed

when input levels of 3.6 volts or less are used. The typical

number of program and erase cycles is in excess of 10,000

cycles.

The optional 8K word boot block section includes a repro-

gramming lock out feature to provide data integrity. The

boot sector is designed to contain user secure code, and

when the feature is enabled, the boot sector is protected

from being reprogrammed.

During a chip erase, sector erase, or word programming,

the V

pin must be at 5V

10%.

Block Diagram

AT49BV/LV8192

AT49BV/LV8192T

GND

RESET

ADDRESS

INPUTS

DATA INPUTS/OUTPUTS

I/O0 - I/O15

DATA INPUTS/OUTPUTS

I/O0 - I/O15

CONTROL

LOGIC

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

Y-GATING

MAIN MEMORY

(488K WORDS)

PARAMETER

BLOCK 2

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

BOOT BLOCK

8K WORDS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

Y-GATING

Y DECODER

X DECODER

7FFFF

06000

05FFF

04000

03FFF

02000

01FFF

00000

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

8K WORDS

PARAMETER

BLOCK 2

8K WORDS

MAIN MEMORY

(488K WORDS)

7FFFF

7E000

7DFFF

7C000

7BFFF

7A000

79FFF

00000

Device Operation

READ:

The AT49BV/LV8192 is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

COMMAND SEQUENCES:

When the device is first pow-

ered on it will be reset to the read or standby mode

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table

(I/O8 - I/O15 are don't care inputs for the command codes).

The command sequences are written by applying a low

pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

RESET:

A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high impedance state. When

a high level is reasserted on the RESET pin, the device

returns to the Read or Standby mode, depending upon the

state of the control inputs. By applying a 12V

0.5V input

AT49BV/LV8192(T)

AT49BV/LV8192(T)

signal to the RESET pin the boot block array can be repro-

grammed even if the boot block program lockout feature

has been enabled (see Boot Block Programming Lockout

Override section).

ERASURE:

Before a word can be reprogrammed, it must

be erased. The erased state of memory bits is a logical “1”.

The entire device can be erased by using the Chip Erase

command or individual sectors can be erased by using the

Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one

time by using the 6-byte chip erase software code. After the

chip erase has been initiated, the device will internally time

the erase operation so that no external clocks are required.

The maximum time to erease the chip is t

If the boot block lockout has been enabled, the Chip Erase

will not erase the data in the boot block; it will erase the

main memory block and the parameter blocks only. After

the chip erase, the device will return to the read or standby

mode.

SECTOR ERASE:

As an alternative to a full chip erase,

the device is organized into three sectors that can be indi-

vidually erased. There are two 8K word parameter block

sections and one sector consisting of the boot block and

the main memory array block. The Sector Erase command

is a six bus cycle operation. The sector address is latched

on the falling WE edge of the sixth cycle while the 30H data

input command is latched at the rising edge of WE. The

sector erase starts after the rising edge of WE of the sixth

cycle. The erase operation is internally controlled; it will

automatically time to completion. When the boot block pro-

gramming lockout feature is not enabled, the boot block

and the main memory block will erase together (from the

same sector erase command). Once the boot region has

been protected, only the main memory array sector will

erase when its sector erase command is issued.

WORD PROGRAMMING:

Once a memory block is

erased, it is programmed (to a logical “0”) on a word-by-

word basis. Programming is accomplished via the internal

device command register and is a 4 bus cycle operation.

The device will automatically generate the required internal

program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

the specified t

cycle time. The DATA polling feature may

also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 8K words. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block’s usage as a write protected region is

optional to the user. The address range of the

49BV/LV8192 boot block is 00000H to 01FFFH while the

address range of the 49BV/LV8192T is 7E000H to

7FFFFH.

Once the feature is enabled, the data in the boot block can

no longer be erased or programmed when input levels of

5.5V or less are used. Data in the main memory block can

still be changed through the regular programming method.

To activate the lockout feature, a series of six program

commands to specific addresses with specific data must be

performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software

method is available to determine if programming of the boot

block section is locked out. When the device is in the soft-

ware product identification mode (see Software Product

Identification Entry and Exit sections) a read from address

location 00002H will show if programming the boot block is

locked out. If the data on I/O0 is low, the boot block can be

programmed; if the data on I/O0 is high, the program lock-

out feature has been enabled and the block cannot be pro-

grammed. The software product identification exit code

should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVER-

RIDE:

The user can override the boot block programming

lockout by taking the RESET pin to 12 volts during the

entire chip erase, sector erase or word programming oper-

ation. When the RESET pin is brought back to TTL levels

the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION:

The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING:

The AT49BV/LV8192 features DATA

polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte loaded will

result in the complement of the loaded data on I/O7. Once

the program cycle has been completed, true data is valid

on all outputs and the next cycle may begin. During a chip

or sector erase operation, an attempt to read the device will

give a “0” on I/O7. Once the program or erase cycle has

completed, true data will be read from the device. DATA

polling may begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA polling the

AT49BV/LV8192 provides another method for determining

the end of a program or erase cycle. During a program or

erase operation, successive attempts to read data from the

device will result in I/O6 toggling between one and zero.

Once the program cycle has completed, I/O6 will stop tog-

gling and valid data will be read. Examining the toggle bit

may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features

protect against inadvertent programs to the

AT49BV/LV8192 in the following ways: (a) V

sense: if

is below 1.8V (typical), the program function is inhib-

ited. (b) V

power on delay: once V

has reached the

sense level, the device will automatically time out 10

ms (typical) before programming. (c) Program inhibit: hold-

ing any one of OE low, CE high or WE high inhibits pro-

gram cycles. (d) Noise filter: pulses of less than 15 ns (typi-

cal) on the WE or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V

power supply, the address inputs and control inputs (OE,

CE, and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V

+ 0.6V.

AT49BV/LV8192(T)

AT49BV/LV8192(T)

Command Definition (in Hex)

(1)

Command

Sequence

Read

Chip Erase

Sector Erase

Word Program

Boot Block Lockout

(2)

Product ID Entry

Product ID Exit

(3)

Bus

Cycles

1st Bus

Cycle

Addr

5555

Data

OUT

2AAA

5555

Addr

5555

2AAA

5555

2AAA

5555

(4)(5)

2nd Bus

Cycle

Addr

Data

3rd Bus

Cycle

Addr

Data

4th Bus

Cycle

Addr

Data

5th Bus

Cycle

Addr

Data

6th Bus

Cycle

Addr

Data

Product ID Exit

(3)

xxxx

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

2. The 8K word boot sector has the address range 00000H to 01FFFH for the AT49BV/LV8192 and 7E000H to 7FFFFH for the

AT49BV/LV8192T.

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses:

For the AT49BV/LV8192

SA = 03XXX for PARAMETER BLOCK 1

SA = 05XXX for PARAMETER BLOCK 2

SA = 7FXXX for MAIN MEMORY ARRAY

For the AT49BV/LV8192T

SA = 7DXXX for PARAMETER BLOCK 1

SA = 7BXXX for PARAMETER BLOCK 2

SA = 79XXX for MAIN MEMORY ARRAY

5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase

together (form the same sector erase command). Once the boot region has been protected, only the main memory array

sector will erase when its sector erase command is issued.

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on RESET

with Respect to Ground ...................................-0.6V to +13.5V

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.