Features
•
32-Mbit Flash and 4-Mbit/8-Mbit SRAM
•
Single 66-ball 8 mm x 11 mm CBGA Package
•
2.7V to 3.3V Operating Voltage
Flash
•
2.7V to 3.3V Read/Write
•
Access Time – 85, 90, 110 ns
•
Sector Erase Architecture
•
•
•
•
•
•
•
•
•
•
•
– Sixty-three 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 200 ms
Dual-plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word and Fifteen 32K Word Sectors
Memory Plane B: Forty-eight 32K Word Sectors
Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
– 25 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
32-megabit
(2M x 16) Flash
+ 4-megabit
(256K x 16)/
8-megabit
(512K x 16)
SRAM
Stack Memory
AT52BR3244
AT52BR3244T
AT52BR3248
AT52BR3248T
SRAM
•
•
•
•
•
•
4-megabit (256K x 16)/8-megabit (512K x 16)
2.7V to 3.3V V
CC
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
Device Number
Flash Boot Location
Flash Plane
Architecture
SRAM Configuration
AT52BR3244
AT52BR3244T
AT52BR3248
AT52BR3248T
Bottom
Top
Bottom
Top
24M + 8M
24M + 8M
24M + 8M
24M + 8M
256K x 16
256K x 16
512K x 16
512K x 16
Not Recommended for
New Designs. New
Designs Should Use
AT52BR3224(T)/3228(T)
Rev. 2471E–STKD–10/02
1
AT52BR3244(T)/
AT52BR3248(T)
(Top View)
A
B
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A20
A16
A11
A8
A15
A10
A14
A9
A13
D15
D13
D12
A12
SWE
D6
GND
D14
D4
NC
D7
D5
NC
NC
C
WE
RDY/BSY
D
SGND
RESET
SCS2 SVCC VCC
D10
D9
A6
A0
A3
CE
D8
A2
GND
D2
D0
A1
OE
D3
D1
SCS1
NC
NC
NC
E
NC
VPP
SUB
A17
A5
A19
SOE
A7
A4
D11
F
SLB
G
A18
H
NC
NC
NC
Pin Configurations
l
Pin Name
A0 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
VCC
GND
I/O0 - I/O15
NC
SLB
SUB
SVCC
SGND
SCS1
SCS2
SWE
SOE
Function
Addresses
Flash Chip Enable
Flash Output Enable
Flash Write Enable
Flash Reset
Flash READY/BUSY Output
Flash Power Supply for Accelerated Program/Erase Operations
Flash Power
Flash Ground
Data Inputs/Outputs
No Connect
SRAM Lower Byte
SRAM Upper Byte
SRAM Power
SRAM Ground
SRAM Chip Select 1
SRAM Chip Select 2
SRAM Write Enable
SRAM Output Enable
2
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AT52BR3244(T)/3248(T)
Description
The AT52BR3244(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM in a stacked 66-ball CBGA package.
The AT52BR3248(T) combines a 32-megabit Flash (2M x 16) and a 8-megabit SRAM in a stacked 66-ball CBGA package.
The devices operate at 2.7V to 3.3V in the industrial temperature range. They use a 32-megabit Flash with dual plane
architecture for concurrent read/write operations. It is organized as 24M + 8M for planes A and B, respectively. The
4-megabit SRAM is organized as 256K x 16, while the 8-megabit SRAM is organized as 512K x 16.
Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
RDY/BUSY
32-Mbit
FLASH
4/8-Mbit
SRAM
SCS1
SCS2
DATA
Absolute Maximum Ratings
Temperature under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -55°C to +150°C
All Input Voltages
except V
PP
and RESET
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
Voltage on V
PP
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC and AC Operating Range
AT52BR3244(T)-85, -90
AT52BR3248(T)-85, -90
Operating Temperature (Case)
V
CC
Power Supply
Industrial
-40°C - 85°C
2.7V to 3.3V
-40°C - 85°C
2.7V to 3.3V
3
2471E–STKD–10/02
32-megabit Flash
Description
The 32-megabit Flash memory is organized as 2,097,152 words of 16 bits each or
4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data
appears on I/O0 - I/O7. The memory is divided into 71 sectors for erase operations. The
device has CE and OE control signals to avoid any bus contention. This device can be
read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-
system programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the capa-
bility to protect the data in any sector (see Sector Lockdown section).
The device is segmented into two memory planes. Reads from memory plane B may be
performed even while program or erase functions are being executed in memory plane
A and vice versa. This operation allows improved system performance by not requiring
the system to wait for a program or erase operation to complete before a read is per-
formed. To further increase the flexibility of the device, it contains an Erase Suspend
feature. This feature will put the erase on hold for any amount of time and let the user
read data from or program data to any of the remaining sectors within the same memory
plane. There is no reason to suspend the erase operation if the data to be read is in the
other memory plane. The end of a program or an erase cycle is detected by the
Ready/Busy pin, Data Polling or by the toggle bit.
The VPP pin provides faster program/erase times. With V
PP
at 5.0V or 12.0V, the pro-
gram and erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the
requirement of entering the three-byte program sequence is offered to further improve
programming time. After entering the six-byte code, only single pulses on the write con-
trol lines are required for writing into the device. This mode (Single Pulse Word
Program) is exited by powering down the device, or by pulsing the RESET pin low for a
minimum of 50 ns and then bringing it back to V
CC
. Erase and Erase Suspend/Resume
commands will not work while in this mode; if entered they will result in data being pro-
grammed into the device. It is not recommended that the six-byte code reside in the
software of the final product but only exist in external programming code.
4
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AT52BR3244(T)/3248(T)
32-megabit Flash Memory Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A20
INPUT
BUFFER
DATA
REGISTER
IDENTIFIER
REGISTER
STATUS
REGISTER
COMMAND
REGISTER
CE
WE
OE
RESET
ADDRESS
LATCH
DATA
COMPARATOR
RDY/BUSY
WRITE STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
PLANE B
SECTORS
PLANE A SECTORS
5
2471E–STKD–10/02
