Features
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Full-Frame Image Sensor 4096 x 4096 Pixels
11 µm x 11 µm Photo-MOS Pixel with 100% Aperture
Image Zone: 45 x 45 mm
Frame Readout Through One, Two or Four Outputs
Data Rates Up to 4 x 40 MHz (Compatibility with 7, 4 Frames/Second)
True 12-bit High Dynamic Range
Very Low Readout Noise
Very Low Dark Current (MPP Mode)
Optimized Resolution and Responsivity in the 400 - 1100 nm Spectrum
On-chip Thermometer for Each Quarter
Additional Full-Frame Operating Modes:
– 4/3 Aspect Ratio: 4096 x 3072
– 2/1 Aspect Ratio: 4096 x 2048
– Binning 2 x 2 Pixels (Format 2048 x 2048 Pixels of 22 x 22 µm)
– Binning 4 x 4 Pixels (Format 1024x 1024 Pixels of 44 x 44 µm)
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On-request Frame Transfer Architecture:
– 2048 Active Lines, One Memory Zone with Frame Readout Through One or Two
Outputs
– 2048 Active Lines, Two Memories Zones with Frame Readout Through Two or Four
Outputs
16 M-Pixels
Sensor
AT71201M
Preliminary
Applications
Flexibility and performance makes this device suitable for digital photography, graphic
arts, medical or industrial applications and scientific analysis.
Description
Atmel's AT71201M is a full-frame sensor based on charge-coupled device (CCD)
technology. It can be used in a wide range of applications thanks to operating mode
flexibility, very high definition and high dynamic range.
The nominal photosensitive area is made up of 4096 x 4096 useful pixels and is split
into four independent zones that are driven separately by four independent four-phase
clock sets. Thus the sensor can be used in up to 12 main modes.
The large format and high definition make the device suitable for any application
requiring precision.
The high sensitivity of the 11 x 11 µm pixels with 100% fill factor provides a large
bandwidth of response with up to 1100 nm wavelength.
Two serial registers and four independent output amplifiers offer a high-frequency
functionality at 40 MSPS and up to 7.4 frames per second with a high signal to noise
ratio.
Rev. 5328A–IMAGE–05/03
1
Pinout
Figure 1.
AT71201M Pinout, Top View of the Sensor
2
2
25
24
1
A
A
B
Output 3
Output 1
VS1
C
VOS1
PHILS1
VTHH1
PHILA6
PHILA5
PHITA
VSS2
PHIPB1
PHIPA1
PHIPA3
PHIPB3
VSS2
VSS1
PHILA1
PHILA2
VTHH2
PHILS2
Output 2
VOS2
VS2
VDR2
24
VGS1
VTHL1
VSS2
PHILA8
PHILA7
VDEA
PHIPB2
PHIPA2
PHIPA4
PHIPB4
PHIFCA
PHILA3
PHILA4
VDE
VTHL2
VGS2
VDD2
PHIR2
VSS3
25
VDD1
PHIR1
D
VSS2
VDR3
VDR1
VSS3
B
PHIR3
VS3
C
VDD3
VOS3
D
AT71201M
E
B Zone
A Zone
D Zone
C Zone
F
G
H
J
K
L
M
REGISTER B
REGISTER A
N
VGS3
PHILS3
E
VTHL3
VTHH3
F
VDE
PHILB2
G
PHILB4
PHILB1
H
PHILB3
VSS1
J
PHIFCB
VSS2
AT71201
K
Output 4
2
PHIPC4
PHIPC3
L
PHIPD4
PHIPD3
M
PHIPD2
PHIPD1
N
PHIPC2
PHIPC1
P
P
VDEB
VSS2
Q
Q
PHILB7
PHITB
R
R
PHILB8
PHILB5
S
S
VSS2
PHILB6
T
T
VTHL4
VTHH4
U
U
VGS4
PHILS4
V
V
VDD4
VOS4
PHIR4
VS4
W
W
X
X
VSS2
VDR4
1
5328A–IMAGE–05/03
AT71201M
Table 1.
AT71201M Pinout
Signal Name
PHILA [1;8]
PHILB [1;8]
PHILS [1;4]
PHIR [1;4]
PHIPA [1;4]
PHIPB [1;4]
PHIPC [1;4]
PHIPD [1;4]
PHITA
VGS [1;4]
VOS [1;4]
VDD [1;4]
VS [1;4]
VDR [1;4]
VDE (2)
VDEA
VDEB
VTHL [1;4]
VTHH [1;4]
VSS (12)
Parameter
Registers A clocks
Registers B clocks
Summing clocks
Reset gates
Image zone A clocks
Image zone B clocks
Image zone C clocks
Image zone D clocks
Image zone to register A transfer clock
Register output gate biases
Video outputs
Amplifier drains
Amplifier sources
Reset drains
Peripheral vertical drain
Peripheral drain along register A
Peripheral drain along register B
Thermometer low 1 to 4
Thermometer high 1 to 4
Ground connection
3
5328A–IMAGE–05/03
Block Diagram
Figure 2.
AT71201M Block Diagram - Top View
ΦLs1
VGS1
ΦR1
VDR1
VS1
VOS1
VDD1
VTHH1
VTHL1
16 Prescans
VDEA
ΦLA1
to 4
ΦLA5
to 8
ΦTA
VS2
VOS2
VDD2
VTHH2
VTHL2
Φ
Ls2
VGS2
Φ
R2
VDR2
ΦTA
ΦPAj
24 vertical
references
ΦPAj
ΦPBj
VDE
4096 x 4096 useful pixels
(11 x 11 µm²) = 45 x 45 mm²
ΦPBj
VDE
ΦPCj
8 vertical & horizontal insulating
elements (including 4 dark ones)
ΦPCj
ΦPDj
ΦPDj
}
}
}
}
A Zone
B Zone
C Zone
D Zone
ΦTB
Φ
Ls3
VGS3
Φ
R3
VDR3
VS3
VOS3
VDD3
VTHH3
VTHL3
ΦLB1
to 4
VDEB
ΦLB5
to 8
VS4
Thermometer
Φ
Ls4
VOS4 VGS4
VDD4
Φ
R4
VTHH4 VDR4
VTHL4
ΦTB
Readout
modes
4
AT71201M
5328A–IMAGE–05/03
AT71201M
Architectural
Overview
General Parameters
Table 2.
General Parameters
Parameter
Pixel size
Number of useful pixels per line
Number of useful lines
Number of extra lines
Number of readout registers
Number of prescan CCD stages (per output)
Number of dark references (cells per line)
Number of outputs (2 per register)
MPP mode/low dark current mode
Anti-blooming functionality
Binning (summation) mode
Pixel clocking mode
Readout Register clocking mode
Specific functions
Notes:
Value
11 x 11 µm²
4096
4096
8 per register
2
16
24
4
(1)
Yes (image zone)
no
Yes
(2)
4-phase
2-phase
Thermometer
1. The full-frame version can be read through one, two or four outputs
2. The lines summation into the register is made by a specific timing diagram. The inte-
gration time should be adapted to prevent charge overflow.
A specific clock allows column summation.
The pixel size is 11 x 11µm
2
with 100% fill factor (photo-MOS technology).
The sensor is compatible with a 180° rotation.
The image zone commands are split in 4 horizontal areas. The combination of the
ΦPij
clocks allows various transfer configurations.
The serial registers are driven by 8
ΦLi
clocks. An adapted combination of them allows
transfers of 100% of stages to the right side or the left side or 50% in each direction.
5
5328A–IMAGE–05/03
