Features
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DC to DC Converter 1.9V / 2.5V (DCDC1)
LDO Regulator 2.7V / 2.8V (LDO1)
LDO Regulator 2.8V (LDO2)
LDO Regulator 2.8V (LDO3)
LDO Regulator 2.47V / 2.66 (LDO4) - Backup Battery Supply
LDO Regulator 1.72V / 2.66 (LDO5) - RTC Supply
Reset Generator
1. Description
The AT73C211 is a power management device for digital, analog, interface, and, in
some cases, RF and backup sections of add-on modules used as accessories in pop-
ular handheld devices like mobile phones, digital still cameras, PDAs and a wide
range of multimedia devices. The AT73C211 can also be used to supply the CPU with
a high-efficiency DC-DC Converter, a radio frequency transceiver with high power
supply rejection ratio (PSRR) and noise performance low-dropout (LDO) regulators, or
memories and analog sections with independent LDO channels.
In addition, the AT73C211 integrates LDO regulators to recharge backup elements
and convert its voltage to microcontroller RTC supply.
LDO regulators and DC-DC converters output voltage can be programmed by a mask
change.
Power
Management
AT73C211
6199A–PMGMT–20-Sep-05
2. Functional Block Diagram
Figure 2-1.
AT73C211 Block Diagram
VPAD
VPAD
VBATT
VBATT
UP-ON/OFF
ON/OFF
EN
POR
UP-ON/OFF
ON/OFF
10KHz
OSC
PMC
State
Machine
LS
SPI
VBATT
>3.2V
RESET
GENERATOR
35ms
State Machine Reset
RESET-B
RESET-B
DGND
LX
VCORE
GND1
GND
en_vcore
en_vpad
CORE DC/ DC
VIN
LP
LX
reset
DCDC
FB
CREF
ECO-MODE
CREF
GND
EN
EN
VCORE
1.9/2.5V / 300 mA
Vref
Over-Temp
EN
GND
ECO-MODE
ANALOG LDO
VIN
VOUT
AVCC
VBATT
AGND
GND
EN-ANALOG-B
AVCC
2.7/ 2.8V / 130 mA
en_vcore
EN
BB1
LDO1
2.8V
GND
AGND
AGND
EN-ANALOG-B
VBATT
VBATT
VIN-REG1
VIN-REG2
PAD LDO
VIN
VOUT
V-PAD
RTC SUPPLY BLOCK
BAT-RTC
2.47 /2.66V
5 mA
VCC-RTC
1.72 /2.66V
0.5mA
GND
GND
BAT-RTC
VCC-RTC
VBACK
VIN
LP
EN
LDO2
GND
GND
V-PAD
2.8V / 80 mA
LDO4
LDO5
2.7V
BB1
DEEP
DISCHARGED
EN
2.6V
GND
BB1
AGND1
GND GND
GND
EN
VVIB
VBATT
VIBRATOR LDO
VIN
VOUT
VIB -OUT
en_vcore
EN-VIB
EN
GND
BB1
TEST
GND
V-VIB
2.8V /130 mA
LDO3
GND
DGND
GND
GND
2
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
3. Pin Description
Table 3-1.
Signal
VBATT
ON/OFF
UP-ON/OFF
RESET-B
VIN-REG1
LX
ECO-MODE
VCORE
GND1
VIN-REG2
EN-ANALOG-B
AVCC
AGND
V-PAD
VCC-RTC
BAT-RTC
VIN-RF
AGND2
VIN-VIB
EN-VIB
VVIB
GND
CREF
BB1
TEST
Pin Description
Pin
E1
D5
C6
F6
G6
F7
G5
G4
G7
A5
B5
B4
A7
B6
B7
A6
A3
A2
D7
E6
E7
D1
C7
D4
E5
Type
VBATT1
IPD
I
OD
VBATT2
O
IPD
O
Ground
VBATT3
IPD
O
Ground
O
O
I/O
VBATT4
Ground
VBATT5
IPD
O
Ground
O
I
IPD
A
D
A
D
A
A
A
A
D
A
A
D
A
D
D
D
A/D
Description
Input supply
Key ON/OFF input, 1.5M Ohm pull-down
Hold the Power ON from MCU
Reset open collector output. Need external pull-up to VBATT
Input supply for DC/DC converter
DC/DC converter output inductor
Eco Mode, from MCU - sets VCORE, V-PAD in low power mode,
1.5M Ohm pull-down
DC/DC converter output (MCU core supply)
Ground of DC/DC converter
Input supply
Enable the analog LDO, active at logic 0, 1.5M Ohm pull-down
Analog LDO output (MCU chip analog supply)
Ground of AVCC, V-PAD and RTC LDO
Digital LDO output (MCU chip digital PAD supply)
MCU RTC supply output
RTC backup battery charger - must be connected through a 2.2K
Ohm resistor to the backup battery
Input supply
Ground
Input supply for vibrator LDO
Vibrator driver input (from baseband chip), 1.5M Ohm pull-down
Vibrator LDO output (Voltage regulator)
Ground
Bandgap decoupling - 100 nF capacitor must be connected from
this pin to ground
BB1 = 1 => VCORE = 2.5V, BB1= 0 => VCORE = 1.9V
Connect to AGND
3
6199A–PMGMT–20-Sep-05
4. Functional Description
4.1
DC to DC Converter 1.9V/2.5V - 300 mA for Coprocessor Core
The DC-to-DC converter is a synchronous mode DC-to-DC “buck”-switched regulator using
fixed-frequency architecture (PWM) and capable of providing 300 mA of continuous current. It
has two levels of voltage programming for the co-processor core (1.9V or 2.5V). The operating
supply range is from 3.1V to 5.5V, making it suitable for Li-Ion, Li-polymer or Ni-MH battery
applications. The DC-to-DC converter is based on pulse width modulation architecture to con-
trol the noise perturbation for switching noise sensitive applications (Wireless). The operating
frequency is set to 900 kHz using an internal clock, allowing the use of a small surface induc-
tor and moderate output voltage ripple. The controller consists of a reference ramp generator,
a feedback comparator, the logic driver used to drive the internal switches, the feedback cir-
cuits used to manage the different modes of operation and the over-current protection circuits.
An economic mode has been defined to reduce quiescent current. A low-dropout voltage reg-
ulator in parallel to the DC-to-DC converter minimizes standby current consumption during
standby mode.
Figure 4-1.
Dual-power DC-to-DC Converter
V
BATT
ECO-MODE
DC-to-DC Buck
1.9V or 2.5V
300 mA
Internal FET
L
V
CORE
LDO
1.9V or 2.5V
10 mA
Low Power
C
Low undershoot voltage is expected when going from PWM to LDO mode and vice-versa. The
circuit is designed in order to avoid any spikes when transition between two modes is enabled.
Figure 4-2.
Low-power/Full-power DC-to-DC Converter Transition
V
CORE
V
CORE
High Power
ECO-MODE
Low Power
ECO-MODE
High Power
Low Power
4
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
Figure 4-3
shows typical efficiency levels of the DC-to-DC converter for several input voltages.
Figure 4-3.
DC-to-DC Converter with 1.9V Target Typical Case
(1)
100
95
Efficiency (%)
90
85
80
75
70
0
50
100
150
200
250
300
350
400
Load Current (m A)
VIN=3.1V
VIN=3.6V
VIN=4.2V
Note:
1. L = 10 µH, ESR = 0.2 Ohm, c = 22 µF, @ESR = 0.1 Ohm
4.2
LDO1, LDO3 Regulators
The PSRR measures the degree of immunity against voltage fluctuations achieved by a regu-
lator. An example of its importance is in the case of a GSM phone when the antenna switch
activates the RF power amplifier (PA). This causes a current peak of up to 2A on the battery,
with an important spike on the battery voltage. The voltage regulator must filter or attenuate
this spike.
5
6199A–PMGMT–20-Sep-05
