Features
•
One of a Family of 9 Devices with User Memories from 1 Kbit to 256-Kbit
•
8-Kbit (1-Kbyte) EEPROM User Memory
⎯
Eight 128-byte (1-Kbit) Zones
⎯
Self-timed Write Cycle
⎯
Single Byte or 16-byte Page Write Mode
⎯
Programmable Access Rights for Each Zone
•
2-Kbit Configuration Zone
⎯
37-byte OTP Area for User-defined Codes
⎯
160-byte Area for User-defined Keys and Passwords
•
High Security Features
⎯
64-bit Mutual Authentication Protocol (Under License of ELVA)
⎯
Encrypted Checksum
⎯
Stream Encryption
⎯
Four Key Sets for Authentication and Encryption
⎯
Eight Sets of Two 24-bit Passwords
⎯
Anti-tearing Function
⎯
Voltage and Frequency Monitor
•
Smart Card Features
⎯
ISO 7816 Class A (5V) or Class B (3V) Operation
⎯
ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus® Patent)
⎯
Multiple Zones, Key Sets and Passwords for Multi-application Use
⎯
Synchronous 2-wire Serial Interface for Faster Device Initialization
⎯
Programmable 8-byte Answer-To-Reset Register
⎯
ISO 7816-2 Compliant Modules
•
Embedded Application Features
⎯
Low Voltage Operation: 2.7V to 5.5V
⎯
Secure Nonvolatile Storage for Sensitive System or User Information
⎯
2-wire Serial Interface
⎯
1.0 MHz Compatibility for Fast Operation
⎯
Standard 8-lead Plastic Packages, Green Compliant (exceeds RoHS)
⎯
Same Pinout as 2-wire Serial EEPROMs
•
High Reliability
⎯
Endurance: 100,000 Cycles
⎯
Data Retention: 10 years
⎯
ESD Protection: 4,000V min
Table 1.
Pad
V
CC
GND
SCL/CLK
Pin Configuration
Description
Supply Voltage
Ground
Serial Clock Input
ISO Module
Contact
C1
C5
C3
Standard
Package Pin
8
4
6
2024JS–SMEM–3/09
CryptoMemory
®
8 Kbit
AT88SC0808C
Summary
Pad
SDA/IO
RST
Figure 1.
Description
Serial Data Input/Output
Reset Input
Package Options
ISO Module
Contact
C7
C2
Standard
Package Pin
5
NC
Smart Card Module
V
CC
=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=SDA/IO
C8=NC
NC
NC
NC
GND
8-lead SOIC, PDIP
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
1.
Description
The AT88SC0808C member of the CryptoMemory
®
family is a high-performance secure memory providing 8 Kbits of
user memory with advanced security and cryptographic features built in. The user memory is divided into 8 128-byte
zones, each of which may be individually set with different security access rights or effectively combined together to
provide space for 1 to 8 data files..
1.1.
Smart Card Applications
The AT88SC0808C provides high security, low cost, and ease of implementation without the need for a microprocessor
operating system. The embedded cryptographic engine provides for dynamic and symmetric mutual authentication
between the device and host, as well as performing stream encryption for all data and passwords exchanged between
the device and host. Up to four unique key sets may be used for these operations. The AT88SC0808C offers the ability
to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined
in ISO 7816-3.
1.2.
Embedded Applications
Through dynamic and symmetric mutual authentication, data encryption, and the use of encrypted checksums, the
AT88SC0808C provides a secure place for storage of sensitive information within a system. With its tamper detection
circuits, this information remains safe even under attack. A 2-wire serial interface running at 1.0 MHz is used for fast
and efficient communications with up to 15 devices that may be individually addressed. The AT88SC0808C is available
in industry standard 8-lead packages with the same familiar pinout as 2-wire serial EEPROMs..
2
AT88SC0808C
2024JS–SMEM–3/09
AT88SC0808C
Figure 2.
Block Diagram
V
CC
GND
Power
Management
Authentication,
Encryption and
Certification Unit
Random
Generator
Synchronous
Interface
Data Transfer
SCL/CLK
SDA/IO
RST
Asynchronous
ISO Interface
Password
Verification
EEPROM
Reset Block
Answer to Reset
2.
2.1.
Pin Descriptions
Supply Voltage (V
CC
)
The V
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
2.2.
Clock (SCL/CLK)
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency
f.
The
nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f. When the
synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge
clock data out of the device.
2.3.
Reset (RST)
The AT88SC0808C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset
sequence is activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal
pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC0808C does not support the synchronous answer-to-reset sequence
2.4.
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of
other open drain or open collector devices. An external pull-up resistor should be connected between SDA and V
CC
.
The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This
rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher
frequency operations while drawing higher average power. SDA/IO information applies to both asynchronous and
synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and
negative edge clock data out of the device.
3
2024JS–SMEM–3/09
Table 2.
DC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V, T
AC
= -40°C to +85°C (unless
otherwise noted)
Symbol
V
CC(2)
I
CC
I
CC
I
CC
I
CC
I
SB
V
IL
(1)
Parameter
Supply Voltage
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Standby Current (V
CC
= 5.5V)
SDA/IO Input Low Threshold
SCL/CLK Input Low Threshold
RST Input Low Threshold
SDA/IO Input High Threshold
SCL/CLK Input High Threshold
RST Input High Threshold
SDA/IO Input Low Current
SCL/CLK Input Low Current
RST Input Low Current
SDA/IO Input High Current
SCL/CLK Input High Current
RST Input High Current
SDA/IO Output High Voltage
SDA/IO Output Low Voltage
SDA/IO Output High Current
Test Condition
Async READ at 3.57MHz
Async WRITE at 3.57MHz
Synch READ at 1MHz
Synch WRITE at 1MHz
V
IN
= V
CC
or GND
Min
2.7
Typ
Max
5.5
5
5
5
5
100
Units
V
mA
mA
mA
mA
mA
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
V
V
μA
0
0
0
V
CC
x 0.7
V
CC
x 0.7
V
CC
x 0.7
0 < V
IL
< V
CC
x 0.15
0 < V
IL
< V
CC
x 0.15
0 < V
IL
< V
CC
x 0.15
V
CC
x 0.7 < V
IH
< V
CC
V
CC
x 0.7 < V
IH
< V
CC
V
CC
x 0.7 < V
IH
< V
CC
20K ohm external pull-up
I
OL
= 1mA
V
OH
V
CC
x 0.7
0
V
CC
x 0.2
V
CC
x 0.2
V
CC
x 0.2
V
CC
V
CC
V
CC
15
15
50
20
100
150
V
CC
V
CC
x 0.15
20
V
IL(1)
V
IL(1)
V
IH(1)(2)
V
IH(1)(2)
V
IH(1)(2)
I
IL
I
IL
I
IL
I
IH
I
IH
I
IH
V
OH
V
OL
I
OH
Notes:
1. V
IL
min and V
IH
max are reference only and are not tested.
2. To prevent Latch Up Conditions from occurring during Power Up of the AT88SCxxxxC, V
CC
must be turned
on before applying V
IH
. For Powering Down, V
IH
must be removed before turning V
CC
off.
4
AT88SC0808C
2024JS–SMEM–3/09
AT88SC0808C
Table 3.
AC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V,
T
AC
= -40°C to +85°C, CL = 30pF (unless
otherwise noted)
Symbol
f
CLK
f
CLK
f
CLK
Parameter
Async Clock Frequency (V
CC
Range: +4.5 - 5.5V)
Async Clock Frequency (V
CC
Range: +2.7 - 3.3V)
Synch Clock Frequency
Clock Duty cycle
t
R
t
F
t
R
t
F
t
AA
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
WR
t
WR
Rise Time - I/O, RST
Fall Time - I/O, RST
Rise Time - CLK
Fall Time - CLK
Clock Low to Data Out Valid
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time (at 25°C)
Write Cycle Time (-40° to +85°C)
200
200
10
100
200
20
5
7
Min
1
1
0
40
Max
5
4
1
60
1
1
9% x period
9% x period
35
Units
MHZ
MHZ
MHZ
%
μS
μS
μS
μS
nS
nS
nS
nS
nS
nS
nS
mS
mS
3.
Device Operation for Synchronous Protocols
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 5 on page 7). Data changes
during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION:
STOP CONDITION:
ACKNOWLEDGE:
A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 6 on page 7).
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 6 on page 7).
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknowledge that it has received each word. This
happens during the ninth clock cycle.
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
MEMORY RESET:
5
2024JS–SMEM–3/09
